/*****************************************************************************
* FUNCTION
* AudDrv_Clk_On / AudDrv_Clk_Off
*
* DESCRIPTION
* Enable/Disable PLL(26M clock) \ AFE clock
*
*****************************************************************************
*/
void AudDrv_Clk_On(void)
{
unsigned long flags;
PRINTK_AUD_CLK("+AudDrv_Clk_On, Aud_AFE_Clk_cntr:%d \n",Aud_AFE_Clk_cntr);
spin_lock_irqsave(&auddrv_Clk_lock, flags);
if (Aud_AFE_Clk_cntr == 0)
{
printk("-----------AudDrv_Clk_On, Aud_AFE_Clk_cntr:%d \n", Aud_AFE_Clk_cntr);
#ifdef PM_MANAGER_API
if (enable_clock(MT_CG_AUDIO_AFE, "AUDIO"))
{
xlog_printk(ANDROID_LOG_ERROR, "Sound", "Aud enable_clock MT_CG_AUDIO_AFE fail !!!\n");
}
#else
Afe_Set_Reg(AUDIO_TOP_CON0, 0x4000, 0x06004044);
#endif
}
Aud_AFE_Clk_cntr++;
spin_unlock_irqrestore(&auddrv_Clk_lock, flags);
PRINTK_AUD_CLK("-AudDrv_Clk_On, Aud_AFE_Clk_cntr:%d \n",Aud_AFE_Clk_cntr);
}
static inline void saradc_power_control(int on)
{
if (on) {
#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8
enable_bandgap();
udelay(10);
#endif
enable_adc();
udelay(5);
enable_clock();
enable_sample_engine();
}
else {
disable_sample_engine();
disable_clock();
disable_adc();
#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8
disable_bandgap();
#endif
}
}
void mt65xx_usb11_clock_enable(bool enable)
{
INFO("mt65xx_usb11_clock_enable++\r\n");
if(enable){
if(clock_enabled)//already enable
return;
else{
enable_clock (MT65XX_PDN_PERI_USB2, "USB11");
clock_enabled = true;
}
}
else{
if(!clock_enabled)//already disabled.
return;
else{
disable_clock (MT65XX_PDN_PERI_USB2, "USB11");
clock_enabled = false;
}
}
return;
}
TVC_STATUS TVC_PowerOn(void)
{
if (!_tvcContext.isTvcPowerOn)
{
BOOL ret;
#if 0 // no need to take care of PLL, because PM will take charge of it
BOOL ret = enable_pll(MT65XX_3G_PLL, "TVC");
ASSERT(!ret);
#endif
ret = enable_clock(MT65XX_PDN_MM_TVC, "TVC");
ASSERT(!ret);
_RestoreTVCRegisters();
_tvcContext.isTvcPowerOn = TRUE;
}
return TVC_STATUS_OK;
}
static int clk_notify(struct notifier_block *nb, unsigned long action,
void *data)
{
int sz, i = 0;
struct device *dev = data;
struct gdsc_notifier_block *gdsc_nb;
struct of_phandle_args clkspec;
struct device_node *np = dev->of_node;
if (!of_find_property(dev->of_node, "power-domains", &sz))
return 0;
gdsc_nb = container_of(nb, struct gdsc_notifier_block, nb);
if (!gdsc_nb->clock_count)
return 0;
switch (action) {
case BUS_NOTIFY_BIND_DRIVER:
while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells",
i, &clkspec)) {
if (match(clkspec.args[0], gdsc_nb->clocks,
gdsc_nb->clock_count))
enable_clock(&clkspec);
i++;
}
break;
case BUS_NOTIFY_UNBOUND_DRIVER:
while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells",
i, &clkspec)) {
if (match(clkspec.args[0], gdsc_nb->clocks,
gdsc_nb->clock_count))
disable_clock(&clkspec);
i++;
}
break;
}
return 0;
}
void AudDrv_ADC2_Clk_On(void)
{
PRINTK_AUD_CLK("+%s %d \n", __func__, Aud_ADC2_Clk_cntr);
mutex_lock(&auddrv_pmic_mutex);
if (Aud_ADC2_Clk_cntr == 0)
{
PRINTK_AUDDRV("+%s enable_clock ADC clk(%x)\n", __func__, Aud_ADC2_Clk_cntr);
#if 0 //K2 removed
#ifdef PM_MANAGER_API
if (enable_clock(MT_CG_AUDIO_ADDA2, "AUDIO"))
{
PRINTK_AUD_CLK("%s fail", __func__);
}
#else
Afe_Set_Reg(AUDIO_TOP_CON0, 0 << 23 , 1 << 23); //temp hard code setting, after confirm with enable clock usage, this could be removed.
#endif
#endif
}
Aud_ADC2_Clk_cntr++;
mutex_unlock(&auddrv_pmic_mutex);
}
void jpeg_drv_dec_power_on(void)
{
//REG_JPEG_MM_REG_MASK = 0;
#ifndef FPGA_VERSION
//enable_clock(MT_CG_IMAGE_JPGD_SMI,"JPEG");
//enable_clock(MT_CG_IMAGE_JPGD_JPG,"JPEG");
#endif
#if 0
//MCI
*(volatile kal_uint32 *)(0xF0208100) |= (0x4|0x8|0x10);
dsb();
*(volatile kal_uint32 *)(0xF0208100) |= (0x11);
dsb();
#endif
#ifdef FOR_COMPILE
BOOL ret;
ret = enable_clock(MT65XX_PDN_MM_JPEG_DEC,"JPEG");
NOT_REFERENCED(ret);
#endif
}
int mali_light_resume(struct device *device)
{
int ret = 0;
/* clock scaling. Kasin..*/
enable_clock();
mali_clock_critical(mali_cri_pmu_on_off, 1);
#ifdef CONFIG_MALI400_PROFILING
_mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE |
MALI_PROFILING_EVENT_CHANNEL_GPU |
MALI_PROFILING_EVENT_REASON_SINGLE_GPU_FREQ_VOLT_CHANGE,
0, 0, 0, 0, 0);
#endif
if (NULL != device->driver &&
NULL != device->driver->pm &&
NULL != device->driver->pm->runtime_resume)
{
/* Need to notify Mali driver about this event */
ret = device->driver->pm->runtime_resume(device);
}
return ret;
}
static int accfix_resume(struct platform_device *dev) // wake up
{
ACCFIX_DEBUG("[accfix]accfix_resume\n");
#ifdef ACCFIX_EINT
if(1==g_accfix_working_in_suspend && 0== call_status)
{
// enable ACCDET unit
OUTREG32(ACCDET_STATE_SWCTRL, pre_state_swctrl);
OUTREG32(ACCDET_CTRL, ACCDET_ENABLE);
//clear g_accfix_working_in_suspend
g_accfix_working_in_suspend =0;
ACCFIX_DEBUG("[accfix]accfix_resume : recovery accfix register\n");
}
#else
if(call_status == 0)
{
enable_clock(MT65XX_PDN_PERI_ACCDET,"ACCFIX");
// enable ACCDET unit
OUTREG32(ACCDET_STATE_SWCTRL, pre_state_swctrl);
OUTREG32(ACCDET_CTRL, ACCDET_ENABLE);
}
#endif
ACCFIX_DEBUG("[accfix]accfix_resume: ACCDET_CTRL=[0x%x]\n", INREG32(ACCDET_CTRL));
ACCFIX_DEBUG("[accfix]accfix_resume: ACCDET_STATE_SWCTRL=[0x%x]\n",
INREG32(ACCDET_STATE_SWCTRL));
ACCFIX_DEBUG("[accfix]resum:sample_in:%x!\n curr_in:%x!\n mem_in:%x!\n FSM:%x!\n"
, INREG32(ACCDET_SAMPLE_IN)
,INREG32(ACCDET_CURR_IN)
,INREG32(ACCDET_MEMORIZED_IN)
,INREG32(ACCDET_BASE + 0x0050));
ACCFIX_DEBUG("[accfix]accfix_resume ok\n");
return 0;
}
INT32 mtk_wcn_consys_hw_reg_ctrl(UINT32 on,UINT32 co_clock_en)
{
INT32 iRet = -1;
UINT32 retry = 10;
UINT32 consysHwChipId = 0;
WMT_PLAT_INFO_FUNC("CONSYS-HW-REG-CTRL(0x%08x),start\n",on);
if(on)
{
#if CONSYS_PMIC_CTRL_ENABLE
/*need PMIC driver provide new API protocol before 1/18/2013*/
/*1.Power on MT6323 VCN_1V8 LDO<--<VCN_1V8>-->write 0 to 0x512[1], write 1 to 0x512[14]*/
upmu_set_vcn_1v8_lp_mode_set(0);
//upmu_set_rg_vcn_1v8_en(1);
/*will be replaced by hwpoweron just as below*/
hwPowerOn(MT6323_POWER_LDO_VCN_1V8,VOL_DEFAULT,"MOD_WMT");
if(co_clock_en)
{
/*2.set VCN_28 to SW control mode<--<VCN28_ON_CTRL>-->write 0 to 0x41C[14]*/
upmu_set_vcn28_on_ctrl(0);
}
else
{
/*2.1.switch VCN28 to HW control mode<--<VCN28_ON_CTRL>-->write 1 to 0x41C[14]*/
upmu_set_vcn28_on_ctrl(1);
/*2.2.turn on VCN28LDO<--<RG_VCN28_EN>-->write 1 to 0x41C[12]*/
//upmu_set_rg_vcn28_en(1);
/*will be replaced by hwpoweron just as below*/
hwPowerOn(MT6323_POWER_LDO_VCN28,VOL_DEFAULT,"MOD_WMT");
}
#endif
/*mask this action and put it into FW patch for resolve ALPS00544691*/
#if 0
/*1.assert CONSYS CPU SW reset, <CONSYS_CPU_SW_RST_REG>, [12] = 1'b1, [31:24]=8'h88(key)--> CONSYS_CPU_SW_RST_BIT | CONSYS_CPU_SW_RST_CTRL_KEY*/
CONSYS_SET_BIT(CONSYS_CPU_SW_RST_REG, CONSYS_CPU_SW_RST_BIT | CONSYS_CPU_SW_RST_CTRL_KEY);
WMT_PLAT_DBG_FUNC("reg uump:CONSYS_CPU_SW_RST_REG(0x%x)\n",CONSYS_REG_READ(CONSYS_CPU_SW_RST_REG));
#endif
#if 0
/*turn on top clock gating enable*/
CONSYS_REG_WRITE(CONSYS_TOP_CLKCG_CLR_REG,CONSYS_REG_READ(CONSYS_TOP_CLKCG_CLR_REG) | CONSYS_TOP_CLKCG_BIT);
WMT_PLAT_DBG_FUNC("reg dump:CONSYS_TOP_CLKCG_CLR_REG(0x%x)\n",CONSYS_REG_READ(CONSYS_TOP_CLKCG_CLR_REG));
/*turn on SPM clock gating enable*/
CONSYS_REG_WRITE(CONSYS_PWRON_CONFG_EN_REG, CONSYS_PWRON_CONFG_EN_VALUE);
WMT_PLAT_DBG_FUNC("reg dump:CONSYS_PWRON_CONFG_EN_REG(0x%x)\n",CONSYS_REG_READ(CONSYS_PWRON_CONFG_EN_REG));
#endif
/*use colck manger API to control MTCMOS*/
conn_power_on();
WMT_PLAT_INFO_FUNC("reg dump:CONSYS_PWR_CONN_ACK_REG(0x%x)\n",CONSYS_REG_READ(CONSYS_PWR_CONN_ACK_REG));
WMT_PLAT_INFO_FUNC("reg dump:CONSYS_PWR_CONN_ACK_S_REG(0x%x)\n",CONSYS_REG_READ(CONSYS_PWR_CONN_ACK_S_REG));
WMT_PLAT_INFO_FUNC("reg dump:CONSYS_TOP1_PWR_CTRL_REG(0x%x)\n",CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG));
/*11.delay 10us, 26M is ready*/
udelay(10);
enable_clock(MT_CG_INFRA_CONNMCU, "WMT_MOD");
/*12.poll CONSYS CHIP until MT6582/MT6572 is returned, <CONSYS_CHIP_ID_REG>, 32'h6582/32'h6572 */
/*what does HW do, why we need to polling this register?*/
while (retry-- > 0)
{
WMT_PLAT_DBG_FUNC("CONSYS_CHIP_ID_REG(0x%08x)",CONSYS_REG_READ(CONSYS_CHIP_ID_REG));
consysHwChipId = CONSYS_REG_READ(CONSYS_CHIP_ID_REG);
if((consysHwChipId == 0x6582) || (consysHwChipId == 0x6572))
{
WMT_PLAT_INFO_FUNC("retry(%d)consys chipId(0x%08x)\n", retry,consysHwChipId);
break;
}
msleep(20);
}
/*mask this action and put it into FW patch for resolve ALPS00544691*/
#if 0
/*13.{default no need}update ROMDEL/PATCH RAM DELSEL if needed, <CONSYS_ROM_RAM_DELSEL_REG>*/
/*14.write 1 to conn_mcu_config ACR[1] if real speed MBIST (default write "1"), <CONSYS_MCU_CFG_ACR_REG>,[18]1'b1-->CONSYS_MCU_CFG_ACR_MBIST_BIT*/
/*if this bit is 0, HW will do memory auto test under low CPU frequence (26M Hz)*/
/*if this bit is 0, HW will do memory auto test under high CPU frequence(138M Hz) inclulding low CPU frequence*/
CONSYS_SET_BIT(CONSYS_MCU_CFG_ACR_REG, CONSYS_MCU_CFG_ACR_MBIST_BIT);
/*15.{default no need, Analog HW will inform if this need to be update or not 1 week after IC sample back}
update ANA_WBG(AFE) CR if needed, CONSYS_AFE_REG */
CONSYS_REG_WRITE(CONSYS_AFE_REG_DIG_RCK_01,CONSYS_AFE_REG_DIG_RCK_01_VALUE);
CONSYS_REG_WRITE(CONSYS_AFE_REG_WBG_PLL_02,CONSYS_AFE_REG_WBG_PLL_02_VALUE);
CONSYS_REG_WRITE(CONSYS_AFE_REG_WBG_WB_TX_01,CONSYS_AFE_REG_WBG_WB_TX_01_VALUE);
/*16.deassert CONSYS CPU SW reset, <CONSYS_CPU_SW_RST_REG>, [12] = 1'b0, [31:24]=8'h88(key)*/
CONSYS_CLR_BIT_WITH_KEY(CONSYS_CPU_SW_RST_REG, CONSYS_CPU_SW_RST_BIT , CONSYS_CPU_SW_RST_CTRL_KEY);
#endif
msleep(5);
iRet = 0;
}else{
disable_clock(MT_CG_INFRA_CONNMCU, "WMT_MOD");
/*New: use colck manger API to control MTCMOS*/
conn_power_off();
#if CONSYS_PMIC_CTRL_ENABLE
/*set VCN_28 to SW control mode*/
upmu_set_vcn28_on_ctrl(0);
/*turn off VCN28 LDO*/
//upmu_set_rg_vcn28_en(0);
/*will be replaced by hwPowerOff*/
hwPowerDown(MT6323_POWER_LDO_VCN28,"MOD_WMT");
/*power off MT6627 VWCN_1V8 LDO*/
upmu_set_vcn_1v8_lp_mode_set(0);
//upmu_set_rg_vcn_1v8_en(0);
/*will be replaced by hwPowerOff*/
hwPowerDown(MT6323_POWER_LDO_VCN_1V8,"MOD_WMT");
#endif
iRet = 0;
}
WMT_PLAT_INFO_FUNC("CONSYS-HW-REG-CTRL(0x%08x),finish\n",on);
return iRet;
}
int disp_bls_config(void)
{
#if !defined(CONFIG_MTK_AAL_SUPPORT)
struct cust_mt65xx_led *cust_led_list = get_cust_led_list();
struct cust_mt65xx_led *cust = NULL;
struct PWM_config *config_data = NULL;
if(cust_led_list)
{
cust = &cust_led_list[MT65XX_LED_TYPE_LCD];
if((strcmp(cust->name,"lcd-backlight") == 0) && (cust->mode == MT65XX_LED_MODE_CUST_BLS_PWM))
{
config_data = &cust->config_data;
if (config_data->clock_source >= 0 && config_data->clock_source <= 3)
{
unsigned int regVal = DISP_REG_GET(CLK_CFG_1);
clkmux_sel(MT_MUX_PWM, config_data->clock_source, "DISP_PWM");
BLS_DBG("disp_bls_init : CLK_CFG_1 0x%x => 0x%x\n", regVal, DISP_REG_GET(CLK_CFG_1));
}
gPWMDiv = (config_data->div == 0) ? PWM_DEFAULT_DIV_VALUE : config_data->div;
gPWMDiv &= 0x3FF;
BLS_MSG("disp_bls_config : PWM config data (%d,%d)\n", config_data->clock_source, config_data->div);
}
}
if (!clock_is_on(MT_CG_DISP0_MDP_BLS_26M) || !gBLSPowerOn)
{
BLS_MSG("disp_bls_config: enable clock\n");
enable_clock(MT_CG_DISP0_SMI_LARB0, "DDP");
enable_clock(MT_CG_DISP0_MDP_BLS_26M , "DDP");
gBLSPowerOn = 1;
}
BLS_MSG("disp_bls_config : BLS_EN=0x%x, PWM_DUTY=%d, PWM_DUTY_RD=%d, CG=0x%x, %d, %d\n",
DISP_REG_GET(DISP_REG_BLS_EN),
DISP_REG_GET(DISP_REG_BLS_PWM_DUTY),
DISP_REG_GET(DISP_REG_BLS_PWM_DUTY_RD),
DISP_REG_GET(DISP_REG_CONFIG_MMSYS_CG_CON0),
clock_is_on(MT_CG_DISP0_MDP_BLS_26M),
clock_is_on(MT_CG_DISP0_DISP_BLS));
#ifdef USE_DISP_BLS_MUTEX
BLS_MSG("disp_bls_config : gBLSMutexID = %d\n", gBLSMutexID);
DISP_REG_SET(DISP_REG_CONFIG_MUTEX_RST(gBLSMutexID), 1);
DISP_REG_SET(DISP_REG_CONFIG_MUTEX_RST(gBLSMutexID), 0);
DISP_REG_SET(DISP_REG_CONFIG_MUTEX_MOD(gBLSMutexID), 0x200); // BLS
DISP_REG_SET(DISP_REG_CONFIG_MUTEX_SOF(gBLSMutexID), 0); // single mode
DISP_REG_SET(DISP_REG_CONFIG_MUTEX_EN(gBLSMutexID), 1);
if (disp_bls_get_mutex() == 0)
{
#else
BLS_MSG("disp_bls_config\n");
DISP_REG_SET(DISP_REG_BLS_DEBUG, 0x3);
#endif
if (!(DISP_REG_GET(DISP_REG_BLS_EN) & 0x10000))
DISP_REG_SET(DISP_REG_BLS_PWM_DUTY, 0);
DISP_REG_SET(DISP_REG_BLS_PWM_CON, 0x0 | (gPWMDiv << 16));
//DISP_REG_SET(DISP_REG_BLS_EN, 0x00010001); //Enable BLS_EN
#ifdef USE_DISP_BLS_MUTEX
if (disp_bls_release_mutex() == 0)
return 0;
}
return -1;
#else
DISP_REG_SET(DISP_REG_BLS_DEBUG, 0x0);
#endif
#endif
BLS_MSG("disp_bls_config:-\n");
return 0;
}
wake_reason_t spm_go_to_dpidle(bool cpu_pdn, u8 pwrlevel)
{
wake_status_t *wakesta;
unsigned long flags;
struct mtk_irq_mask mask;
wake_reason_t wr = WR_NONE;
u32 con0;
u32 top_ckgen_val = 0;
spin_lock_irqsave(&spm_lock, flags);
spm_stop_normal();
mt_irq_mask_all(&mask);
mt_irq_unmask_for_sleep(MT_SPM0_IRQ_ID);
mt_cirq_clone_gic();
mt_cirq_enable();
#ifdef SPM_DPIDLE_SECONDARY_KICK_IMPROVE
if( spm_last_senario != pcm_config_dpidle.scenario)//dpidle SPM Initialize
#endif
{
if(pwrlevel>2)
{
spm_crit2("Hey!! wrong PWR Level: %x",pwrlevel);//ASSERT Wrong Para!!
goto RESTORE_IRQ;
}
pcm_config_dpidle.pcm_pwrlevel = 1 << pwrlevel ;
pcm_config_dpidle.spm_request_uart_sleep = (pwrlevel == 0 ? true : false);
pcm_config_dpidle.cpu_pdn = cpu_pdn;
if (spm_init_pcm(&pcm_config_dpidle)==false)
goto RESTORE_IRQ;
#ifdef SPM_CLOCK_INIT
enable_clock(MT_CG_MEMSLP_DLYER_SW_CG, "SPM_DPIDLE");
enable_clock(MT_CG_SPM_SW_CG, "SPM_DPIDLE");
#endif
#ifdef SPM_DPIDLE_CLK_DBG_OUT
//gpiodbg_monitor();
gpiodbg_emi_dbg_out();
gpiodbg_armcore_dbg_out();
#endif
spm_kick_pcm(&pcm_config_dpidle);
//spm_change_fw = 1;
}
#ifdef SPM_DPIDLE_SECONDARY_KICK_IMPROVE
else
{
if( spm_secondary_kick(&pcm_config_dpidle)==false)
goto RESTORE_IRQ;
//spm_change_fw = 0;
}
#endif
spm_dpidle_before_wfi();
//hopping 33M-->fixed 26M, 20130902 HG.Wei
top_ckgen_val = spm_read(TOPCKGEN_BASE);
spm_write(TOPCKGEN_BASE,top_ckgen_val&(~(1<<26)));
snapshot_golden_setting(__FUNCTION__, __LINE__);
spm_trigger_wfi(&pcm_config_dpidle);
//hopping fixed 26M-->hopping 33M, 20130902 HG.Wei
spm_write(TOPCKGEN_BASE,top_ckgen_val);
spm_dpidle_after_wfi();
wakesta = spm_get_wakeup_status(&pcm_config_dpidle);
wr = wakesta->wake_reason;
spm_clean_after_wakeup();
#ifdef SPM_CLOCK_INIT
disable_clock(MT_CG_SPM_SW_CG, "SPM_DPIDLE");
disable_clock(MT_CG_MEMSLP_DLYER_SW_CG, "SPM_DPIDLE");
#endif
RESTORE_IRQ:
mt_cirq_flush();
mt_cirq_disable();
mt_irq_mask_restore(&mask);
spm_go_to_normal();
spin_unlock_irqrestore(&spm_lock, flags);
return wr;
}
static int pm_callback_power_on(struct kbase_device *kbdev)
{
int touch_boost_flag, touch_boost_id;
unsigned int current_gpu_freq_idx;
#ifndef CONFIG_MTK_CLKMGR
int ret;
#endif
unsigned int code = mt_get_chip_hw_code();
mt_gpufreq_voltage_enable_set(1);
if (0x321 == code) {
// do something for Denali-1(6735)
#ifdef CONFIG_MTK_CLKMGR
enable_clock( MT_CG_DISP0_SMI_COMMON, "GPU");
enable_clock( MT_CG_MFG_BG3D, "GPU");
#else
ret = clk_prepare_enable(kbdev->clk_display_scp);
if (ret)
{
pr_debug("MALI: clk_prepare_enable failed when enabling display MTCMOS");
}
ret = clk_prepare_enable(kbdev->clk_smi_common);
if (ret)
{
pr_debug("MALI: clk_prepare_enable failed when enabling display smi_common clock");
}
ret = clk_prepare_enable(kbdev->clk_mfg_scp);
if (ret)
{
pr_debug("MALI: clk_prepare_enable failed when enabling mfg MTCMOS");
}
ret = clk_prepare_enable(kbdev->clk_mfg);
if (ret)
{
pr_debug("MALI: clk_prepare_enable failed when enabling mfg clock");
}
#endif
} else if (0x335 == code) {
// do something for Denali-2(6735M)
#ifdef CONFIG_MTK_CLKMGR
enable_clock( MT_CG_DISP0_SMI_COMMON, "GPU");
enable_clock( MT_CG_MFG_BG3D, "GPU");
#endif /* CONFIG_MTK_CLKMGR */
} else if (0x337 == code) {
// do something for Denali-3(6753)
#ifdef CONFIG_MTK_CLKMGR
enable_clock( MT_CG_DISP0_SMI_COMMON, "GPU");
enable_clock( MT_CG_MFG_BG3D, "GPU");
#endif /* CONFIG_MTK_CLKMGR */
} else {
// unknown chip ID, error !!
#ifdef CONFIG_MTK_CLKMGR
enable_clock( MT_CG_DISP0_SMI_COMMON, "GPU");
enable_clock( MT_CG_MFG_BG3D, "GPU");
#endif /* CONFIG_MTK_CLKMGR */
}
g_power_status = 1; // the power status is "power on".
mt_gpufreq_target(g_power_off_gpu_freq_idx);
current_gpu_freq_idx = mt_gpufreq_get_cur_freq_index();
if( current_gpu_freq_idx > g_power_off_gpu_freq_idx)
pr_debug("MALI: GPU freq. can't switch to idx=%d\n", g_power_off_gpu_freq_idx );
mtk_get_touch_boost_flag( &touch_boost_flag, &touch_boost_id);
if(g_type_T==1)
{
if(touch_boost_flag > 0)
{
mt_gpufreq_target(1);
mtk_clear_touch_boost_flag();
}
}
else
{
if(touch_boost_flag > 0)
{
mt_gpufreq_target(touch_boost_id);
mtk_clear_touch_boost_flag();
}
}
/* Nothing is needed on VExpress, but we may have destroyed GPU state (if the below HARD_RESET code is active) */
return 1;
}
static int simple_sd_ioctl_get_driving(struct msdc_ioctl* msdc_ctl)
{
u32 base;
// unsigned int l_value;
if (msdc_ctl->host_num == 0){
#ifndef CFG_DEV_MSDC0
printk("host%d is not config\n", msdc_ctl->host_num);
return -1;
#endif
} else if (msdc_ctl->host_num == 1) {
#ifndef CFG_DEV_MSDC1
printk("host%d is not config\n", msdc_ctl->host_num);
return -1;
#endif
} else if (msdc_ctl->host_num == 2) {
#ifndef CFG_DEV_MSDC2
printk("host%d is not config\n", msdc_ctl->host_num);
return -1;
#endif
} else if (msdc_ctl->host_num == 3) {
#ifndef CFG_DEV_MSDC3
printk("host%d is not config\n", msdc_ctl->host_num);
return -1;
#endif
} else if (msdc_ctl->host_num == 4) {
#ifndef CFG_DEV_MSDC4
printk("host%d is not config\n", msdc_ctl->host_num);
return -1;
#endif
}
base = mtk_msdc_host[msdc_ctl->host_num]->base;
#ifndef FPGA_PLATFORM
enable_clock(MT_CG_PERI_MSDC30_0 + mtk_msdc_host[msdc_ctl->host_num]->id, "SD");
#endif
//sdr_get_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKDRVN, l_value);
msdc_ctl->clk_pu_driving = (msdc_dump_padctl0(msdc_ctl->host_num) & 0x7);
//sdr_get_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKDRVP, l_value);
//msdc_ctl->clk_pu_driving = l_value;
//sdr_get_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDDRVN, l_value);
//msdc_ctl->cmd_pd_driving = l_value;
//sdr_get_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDDRVP, l_value);
msdc_ctl->cmd_pu_driving = (msdc_dump_padctl1(msdc_ctl->host_num) & 0x7);
//sdr_get_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATDRVN, l_value);
//msdc_ctl->dat_pd_driving = l_value;
//sdr_get_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATDRVP, l_value);
msdc_ctl->dat_pu_driving = (msdc_dump_padctl2(msdc_ctl->host_num) & 0x7);
#if DEBUG_MMC_IOCTL
//printk("read: clk pull down driving is 0x%x\n", msdc_ctl->clk_pd_driving);
printk("read: clk driving is 0x%x\n", msdc_ctl->clk_pu_driving);
//printk("read: cmd pull down driving is 0x%x\n", msdc_ctl->cmd_pd_driving);
printk("read: cmd driving is 0x%x\n", msdc_ctl->cmd_pu_driving);
//printk("read: dat pull down driving is 0x%x\n", msdc_ctl->dat_pd_driving);
printk("read: dat driving is 0x%x\n", msdc_ctl->dat_pu_driving);
#endif
return 0;
}
static int aal_clock_on(DISP_MODULE_ENUM module, void *cmq_handle)
{
enable_clock(MT_CG_DISP0_DISP_AAL, "aal");
AAL_DBG("aal_clock_on CG 0x%x", DISP_REG_GET(DISP_REG_CONFIG_MMSYS_CG_CON0));
return 0;
}
static int simple_sd_ioctl_get_driving(struct msdc_ioctl *msdc_ctl)
{
void __iomem *base;
/* unsigned int l_value; */
struct msdc_host *host;
if(!msdc_ctl)
return -EINVAL;
if((msdc_ctl->host_num < 0) || (msdc_ctl->host_num >= HOST_MAX_NUM)){
pr_err("invalid host num: %d\n", msdc_ctl->host_num);
return -EINVAL;
}else if (msdc_ctl->host_num == 0){
#ifndef CFG_DEV_MSDC0
pr_err("host%d is not config\n", msdc_ctl->host_num);
return -EINVAL;
#endif
} else if (msdc_ctl->host_num == 1) {
#ifndef CFG_DEV_MSDC1
pr_err("host%d is not config\n", msdc_ctl->host_num);
return -EINVAL;
#endif
} else if (msdc_ctl->host_num == 2) {
#ifndef CFG_DEV_MSDC2
pr_err("host%d is not config\n", msdc_ctl->host_num);
return -EINVAL;
#endif
} else if (msdc_ctl->host_num == 3) {
#ifndef CFG_DEV_MSDC3
pr_err("host%d is not config\n", msdc_ctl->host_num);
return -EINVAL;
#endif
} else if (msdc_ctl->host_num == 4) {
#ifndef CFG_DEV_MSDC4
pr_err("host%d is not config\n", msdc_ctl->host_num);
return -EINVAL;
#endif
}else {
pr_err("invalid host num: %d\n", msdc_ctl->host_num);
return -EINVAL;
}
host = mtk_msdc_host[msdc_ctl->host_num];
BUG_ON(!host);
base = host->base;
#ifndef FPGA_PLATFORM
#ifdef CONFIG_MTK_LEGACY
enable_clock(MT_CG_PERI_MSDC30_0 + host->id, "SD");
#else
clk_enable(host->clock_control);
#endif
msdc_get_driving(mtk_msdc_host[msdc_ctl->host_num], msdc_ctl);
#if DEBUG_MMC_IOCTL
pr_debug("read: clk driving is 0x%x\n", msdc_ctl->clk_pu_driving);
pr_debug("read: cmd driving is 0x%x\n", msdc_ctl->cmd_pu_driving);
pr_debug("read: dat driving is 0x%x\n", msdc_ctl->dat_pu_driving);
pr_debug("read: rst driving is 0x%x\n", msdc_ctl->rst_pu_driving);
pr_debug("read: ds driving is 0x%x\n", msdc_ctl->ds_pu_driving);
#endif
#endif
return 0;
}
void mali_platform_power_mode_change(mali_power_mode power_mode)
{
#if 0
unsigned long flags;
switch (power_mode)
{
case MALI_POWER_MODE_ON:
MALI_DEBUG_PRINT(3, ("Mali platform: Got MALI_POWER_MODE_ON event, %s\n",
atomic_read((atomic_t *)&bPoweroff) ? "powering on" : "already on"));
if (atomic_read((atomic_t *)&bPoweroff) == 1)
{
MALI_DEBUG_PRINT(3,("[+]MFG enable_clock \n"));
mfg_pwr_lock(flags);
//trace_printk("[GPU power] MFG ON\n");
if (!clock_is_on(MT_CG_MFG_G3D))
{
if(_need_univpll) {
enable_pll_spec(UNIVPLL, "GPU");
}
enable_clock(MT_CG_DISP0_SMI_COMMON, "MFG");
enable_clock(MT_CG_MFG_G3D, "MFG");
if(_need_univpll) {
clkmux_sel(MT_MUX_MFG, 6, "GPU");
}
}
mfg_pwr_unlock(flags);
MALI_DEBUG_PRINT(3,("[-]MFG enable_clock \n"));
#if defined(CONFIG_MALI400_PROFILING)
_mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE |
MALI_PROFILING_EVENT_CHANNEL_GPU |
MALI_PROFILING_EVENT_REASON_SINGLE_GPU_FREQ_VOLT_CHANGE, 500,
1200/1000, 0, 0, 0);
#endif
atomic_set((atomic_t *)&bPoweroff, 0);
}
break;
case MALI_POWER_MODE_LIGHT_SLEEP:
case MALI_POWER_MODE_DEEP_SLEEP:
MALI_DEBUG_PRINT(3, ("Mali platform: Got %s event, %s\n", power_mode ==
MALI_POWER_MODE_LIGHT_SLEEP ? "MALI_POWER_MODE_LIGHT_SLEEP" :
"MALI_POWER_MODE_DEEP_SLEEP", atomic_read((atomic_t *)&bPoweroff) ? "already off" : "powering off"));
if (atomic_read((atomic_t *)&bPoweroff) == 0)
{
MALI_DEBUG_PRINT(3,("[+]MFG disable_clock \n"));
mfg_pwr_lock(flags);
//trace_printk("[GPU power] MFG OFF\n");
if (clock_is_on(MT_CG_MFG_G3D))
{
disable_clock(MT_CG_MFG_G3D, "MFG");
disable_clock(MT_CG_DISP0_SMI_COMMON, "MFG");
if(_need_univpll) {
disable_pll_spec(UNIVPLL, "GPU");
}
}
mfg_pwr_unlock(flags);
MALI_DEBUG_PRINT(3,("[-]MFG disable_clock \n"));
#if defined(CONFIG_MALI400_PROFILING)
_mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE |
MALI_PROFILING_EVENT_CHANNEL_GPU |
MALI_PROFILING_EVENT_REASON_SINGLE_GPU_FREQ_VOLT_CHANGE, 0, 0, 0, 0, 0);
#endif
atomic_set((atomic_t *)&bPoweroff, 1);
}
break;
}
#endif
}
static void spm_i2c_control(u32 channel, bool onoff)
{
static int pdn = 0;
static bool i2c_onoff = 0;
#ifdef CONFIG_OF
void __iomem *base;
#else
u32 base;
#endif
u32 i2c_clk;
switch(channel)
{
case 0:
#ifdef CONFIG_OF
base = SPM_I2C0_BASE;
#else
base = I2C0_BASE;
#endif
i2c_clk = MT_CG_PERI_I2C0;
break;
case 1:
#ifdef CONFIG_OF
base = SPM_I2C1_BASE;
#else
base = I2C1_BASE;
#endif
i2c_clk = MT_CG_PERI_I2C1;
break;
case 2:
#ifdef CONFIG_OF
base = SPM_I2C2_BASE;
#else
base = I2C2_BASE;
#endif
i2c_clk = MT_CG_PERI_I2C2;
break;
case 3:
#ifdef CONFIG_OF
base = SPM_I2C3_BASE;
#else
base = I2C3_BASE;
#endif
i2c_clk = MT_CG_PERI_I2C3;
break;
//FIXME: I2C4 is defined in 6595 dts but not in 6795 dts.
#if 0
case 4:
base = I2C4_BASE;
i2c_clk = MT_CG_PERI_I2C4;
break;
#endif
default:
break;
}
if ((1 == onoff) && (0 == i2c_onoff))
{
i2c_onoff = 1;
#if 1
pdn = spm_read(PERI_PDN0_STA) & (1U << i2c_clk);
spm_write(PERI_PDN0_CLR, pdn); /* power on I2C */
#else
pdn = clock_is_on(i2c_clk);
if (!pdn)
enable_clock(i2c_clk, "spm_i2c");
#endif
spm_write(base + OFFSET_CONTROL, 0x0); /* init I2C_CONTROL */
spm_write(base + OFFSET_TRANSAC_LEN, 0x1); /* init I2C_TRANSAC_LEN */
spm_write(base + OFFSET_EXT_CONF, 0x1800); /* init I2C_EXT_CONF */
spm_write(base + OFFSET_IO_CONFIG, 0x3); /* init I2C_IO_CONFIG */
spm_write(base + OFFSET_HS, 0x102); /* init I2C_HS */
}
else
if ((0 == onoff) && (1 == i2c_onoff))
{
i2c_onoff = 0;
#if 1
spm_write(PERI_PDN0_SET, pdn); /* restore I2C power */
#else
if (!pdn)
disable_clock(i2c_clk, "spm_i2c");
#endif
}
else
ASSERT(1);
}
static int simple_sd_ioctl_set_driving(struct msdc_ioctl *msdc_ctl)
{
void __iomem *base;
struct msdc_host *host;
#if DEBUG_MMC_IOCTL
unsigned int l_value;
#endif
if(!msdc_ctl)
return -EINVAL;
if((msdc_ctl->host_num < 0) || (msdc_ctl->host_num >= HOST_MAX_NUM)){
pr_err("invalid host num: %d\n", msdc_ctl->host_num);
return -EINVAL;
}else if (msdc_ctl->host_num == 0){
#ifndef CFG_DEV_MSDC0
pr_err("host%d is not config\n", msdc_ctl->host_num);
return -EINVAL;
#endif
} else if (msdc_ctl->host_num == 1) {
#ifndef CFG_DEV_MSDC1
pr_err("host%d is not config\n", msdc_ctl->host_num);
return -EINVAL;
#endif
} else if (msdc_ctl->host_num == 2) {
#ifndef CFG_DEV_MSDC2
pr_err("host%d is not config\n", msdc_ctl->host_num);
return -EINVAL;
#endif
} else if (msdc_ctl->host_num == 3) {
#ifndef CFG_DEV_MSDC3
pr_err("host%d is not config\n", msdc_ctl->host_num);
return -EINVAL;
#endif
} else if (msdc_ctl->host_num == 4) {
#ifndef CFG_DEV_MSDC4
pr_err("host%d is not config\n", msdc_ctl->host_num);
return -EINVAL;
#endif
}else {
pr_err("invalid host num: %d\n", msdc_ctl->host_num);
return -EINVAL;
}
host = mtk_msdc_host[msdc_ctl->host_num];
BUG_ON(!host);
base = host->base;
#ifndef FPGA_PLATFORM
enable_clock(MT_CG_PERI_MSDC30_0 + host->id, "SD");
#if DEBUG_MMC_IOCTL
pr_debug("set: clk driving is 0x%x\n", msdc_ctl->clk_pu_driving);
pr_debug("set: cmd driving is 0x%x\n", msdc_ctl->cmd_pu_driving);
pr_debug("set: dat driving is 0x%x\n", msdc_ctl->dat_pu_driving);
pr_debug("set: rst driving is 0x%x\n", msdc_ctl->rst_pu_driving);
pr_debug("set: ds driving is 0x%x\n", msdc_ctl->ds_pu_driving);
#endif
host->hw->clk_drv = msdc_ctl->clk_pu_driving;
host->hw->cmd_drv = msdc_ctl->cmd_pu_driving;
host->hw->dat_drv = msdc_ctl->dat_pu_driving;
host->hw->rst_drv = msdc_ctl->rst_pu_driving;
host->hw->ds_drv = msdc_ctl->ds_pu_driving;
host->hw->clk_drv_sd_18 = msdc_ctl->clk_pu_driving;
host->hw->cmd_drv_sd_18 = msdc_ctl->cmd_pu_driving;
host->hw->dat_drv_sd_18 = msdc_ctl->dat_pu_driving;
msdc_set_driving(host, host->hw, 0);
#if DEBUG_MMC_IOCTL
#if 0
msdc_dump_padctl(host);
#endif
#endif
#endif
return 0;
}
INT32 mtk_wcn_consys_hw_reg_ctrl(UINT32 on, UINT32 co_clock_type)
{
INT32 iRet = -1;
UINT32 retry = 10;
UINT32 consysHwChipId = 0;
WMT_PLAT_WARN_FUNC("CONSYS-HW-REG-CTRL(0x%08x),start\n", on);
if (on) {
WMT_PLAT_DBG_FUNC("++\n");
/*step1.PMIC ctrl*/
#if CONSYS_PMIC_CTRL_ENABLE
/*need PMIC driver provide new API protocol */
/*1.AP power on VCN_1V8 LDO (with PMIC_WRAP API) VCN_1V8 */
pmic_set_register_value(PMIC_RG_VCN18_ON_CTRL, 0);
/* VOL_DEFAULT, VOL_1200, VOL_1300, VOL_1500, VOL_1800... */
#if defined(CONFIG_MTK_PMIC_LEGACY)
hwPowerOn(MT6328_POWER_LDO_VCN18, VOL_1800, "wcn_drv");
#else
if (reg_VCN18) {
regulator_set_voltage(reg_VCN18, VOL_1800, VOL_1800);
if (regulator_enable(reg_VCN18))
WMT_PLAT_ERR_FUNC("enable VCN18 fail\n");
else
WMT_PLAT_DBG_FUNC("enable VCN18 ok\n");
}
#endif
udelay(150);
if (co_clock_type) {
/*step0,clk buf ctrl */
WMT_PLAT_INFO_FUNC("co clock type(%d),turn on clk buf\n", co_clock_type);
#if CONSYS_CLOCK_BUF_CTRL
clk_buf_ctrl(CLK_BUF_CONN, 1);
#endif
/*if co-clock mode: */
/*2.set VCN28 to SW control mode (with PMIC_WRAP API) */
/*turn on VCN28 LDO only when FMSYS is activated" */
pmic_set_register_value(PMIC_RG_VCN28_ON_CTRL, 0);
} else {
/*if NOT co-clock: */
/*2.1.switch VCN28 to HW control mode (with PMIC_WRAP API) */
pmic_set_register_value(PMIC_RG_VCN28_ON_CTRL, 1);
/*2.2.turn on VCN28 LDO (with PMIC_WRAP API)" */
/*fix vcn28 not balance warning */
#if defined(CONFIG_MTK_PMIC_LEGACY)
hwPowerOn(MT6328_POWER_LDO_VCN28, VOL_2800, "wcn_drv");
#else
if (reg_VCN28) {
regulator_set_voltage(reg_VCN28, VOL_2800, VOL_2800);
if (regulator_enable(reg_VCN28))
WMT_PLAT_ERR_FUNC("enable VCN_2V8 fail!\n");
else
WMT_PLAT_DBG_FUNC("enable VCN_2V8 ok\n");
}
#endif
}
#endif
/*step2.MTCMOS ctrl*/
#ifdef CONFIG_OF /*use DT */
/*3.assert CONNSYS CPU SW reset 0x10007018 "[12]=1'b1 [31:24]=8'h88 (key)" */
CONSYS_REG_WRITE((conn_reg.ap_rgu_base + CONSYS_CPU_SW_RST_OFFSET),
CONSYS_REG_READ(conn_reg.ap_rgu_base + CONSYS_CPU_SW_RST_OFFSET) |
CONSYS_CPU_SW_RST_BIT | CONSYS_CPU_SW_RST_CTRL_KEY);
/*turn on SPM clock gating enable PWRON_CONFG_EN 0x10006000 32'h0b160001 */
CONSYS_REG_WRITE((conn_reg.spm_base + CONSYS_PWRON_CONFG_EN_OFFSET), CONSYS_PWRON_CONFG_EN_VALUE);
#if CONSYS_PWR_ON_OFF_API_AVAILABLE
#if defined(CONFIG_MTK_CLKMGR)
iRet = conn_power_on(); /* consult clkmgr owner. */
if (iRet)
WMT_PLAT_ERR_FUNC("conn_power_on fail(%d)\n", iRet);
WMT_PLAT_DBG_FUNC("conn_power_on ok\n");
#else
iRet = clk_prepare_enable(clk_scp_conn_main);
if (iRet)
WMT_PLAT_ERR_FUNC("clk_prepare_enable(clk_scp_conn_main) fail(%d)\n", iRet);
WMT_PLAT_DBG_FUNC("clk_prepare_enable(clk_scp_conn_main) ok\n");
#endif /* defined(CONFIG_MTK_CLKMGR) */
#else
/*2.write conn_top1_pwr_on=1, power on conn_top1 0x10006280 [2] 1'b1 */
CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET,
CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) |
CONSYS_SPM_PWR_ON_BIT);
/*3.read conn_top1_pwr_on_ack =1, power on ack ready 0x1000660C [1] */
while (0 == (CONSYS_PWR_ON_ACK_BIT & CONSYS_REG_READ(conn_reg.spm_base + CONSYS_PWR_CONN_ACK_OFFSET)))
NULL;
/*5.write conn_top1_pwr_on_s=1, power on conn_top1 0x10006280 [3] 1'b1 */
CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET,
CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) |
CONSYS_SPM_PWR_ON_S_BIT);
/*6.write conn_clk_dis=0, enable connsys clock 0x10006280 [4] 1'b0 */
CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET,
CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) &
~CONSYS_CLK_CTRL_BIT);
/*7.wait 1us */
udelay(1);
/*8.read conn_top1_pwr_on_ack_s =1, power on ack ready 0x10006610 [1] */
while (0 == (CONSYS_PWR_CONN_ACK_S_BIT &
CONSYS_REG_READ(conn_reg.spm_base + CONSYS_PWR_CONN_ACK_S_OFFSET)))
NULL;
/*9.release connsys ISO, conn_top1_iso_en=0 0x10006280 [1] 1'b0 */
CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET,
CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) &
~CONSYS_SPM_PWR_ISO_S_BIT);
/*10.release SW reset of connsys, conn_ap_sw_rst_b=1 0x10006280[0] 1'b1 */
CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET,
CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) |
CONSYS_SPM_PWR_RST_BIT);
/*disable AXI BUS protect */
CONSYS_REG_WRITE(conn_reg.topckgen_base + CONSYS_TOPAXI_PROT_EN_OFFSET,
CONSYS_REG_READ(conn_reg.topckgen_base + CONSYS_TOPAXI_PROT_EN_OFFSET) &
~CONSYS_PROT_MASK);
while (CONSYS_REG_READ(conn_reg.topckgen_base + CONSYS_TOPAXI_PROT_STA1_OFFSET) & CONSYS_PROT_MASK)
NULL;
#endif
/*11.26M is ready now, delay 10us for mem_pd de-assert */
udelay(10);
/*enable AP bus clock : connmcu_bus_pd API: enable_clock() ++?? */
#if CONSYS_AHB_CLK_MAGEMENT
#if defined(CONFIG_MTK_CLKMGR)
enable_clock(MT_CG_INFRA_CONNMCU_BUS, "WCN_MOD");
WMT_PLAT_DBG_FUNC("enable MT_CG_INFRA_CONNMCU_BUS CLK\n");
#else
iRet = clk_prepare_enable(clk_infra_conn_main);
if (iRet)
WMT_PLAT_ERR_FUNC("clk_prepare_enable(clk_infra_conn_main) fail(%d)\n", iRet);
WMT_PLAT_DBG_FUNC("[CCF]enable clk_infra_conn_main\n");
#endif /* defined(CONFIG_MTK_CLKMGR) */
#endif
/*12.poll CONNSYS CHIP ID until chipid is returned 0x18070008 */
while (retry-- > 0) {
consysHwChipId = CONSYS_REG_READ(conn_reg.mcu_base + CONSYS_CHIP_ID_OFFSET);
if ((consysHwChipId == 0x0321) || (consysHwChipId == 0x0335) || (consysHwChipId == 0x0337)) {
WMT_PLAT_INFO_FUNC("retry(%d)consys chipId(0x%08x)\n", retry, consysHwChipId);
break;
}
WMT_PLAT_ERR_FUNC("Read CONSYS chipId(0x%08x)", consysHwChipId);
msleep(20);
}
if ((0 == retry) || (0 == consysHwChipId)) {
WMT_PLAT_ERR_FUNC("Maybe has a consys power on issue,(0x%08x)\n", consysHwChipId);
WMT_PLAT_ERR_FUNC("reg dump:CONSYS_CPU_SW_RST_REG(0x%x)\n",
CONSYS_REG_READ(conn_reg.ap_rgu_base + CONSYS_CPU_SW_RST_OFFSET));
WMT_PLAT_ERR_FUNC("reg dump:CONSYS_PWR_CONN_ACK_REG(0x%x)\n",
CONSYS_REG_READ(conn_reg.spm_base + CONSYS_PWR_CONN_ACK_OFFSET));
WMT_PLAT_ERR_FUNC("reg dump:CONSYS_PWR_CONN_ACK_S_REG(0x%x)\n",
CONSYS_REG_READ(conn_reg.spm_base + CONSYS_PWR_CONN_ACK_S_OFFSET));
WMT_PLAT_ERR_FUNC("reg dump:CONSYS_TOP1_PWR_CTRL_REG(0x%x)\n",
CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET));
}
/*13.{default no need}update ROMDEL/PATCH RAM DELSEL if needed 0x18070114 */
/*
*14.write 1 to conn_mcu_confg ACR[1] if real speed MBIST
*(default write "1") ACR 0x18070110[18] 1'b1
*if this bit is 0, HW will do memory auto test under low CPU frequence (26M Hz)
*if this bit is 0, HW will do memory auto test under high CPU frequence(138M Hz)
*inclulding low CPU frequence
*/
CONSYS_REG_WRITE(conn_reg.mcu_base + CONSYS_MCU_CFG_ACR_OFFSET,
CONSYS_REG_READ(conn_reg.mcu_base + CONSYS_MCU_CFG_ACR_OFFSET) |
CONSYS_MCU_CFG_ACR_MBIST_BIT);
#if 0
/*15.default no need,update ANA_WBG(AFE) CR if needed, CONSYS_AFE_REG */
CONSYS_REG_WRITE(CONSYS_AFE_REG_DIG_RCK_01, CONSYS_AFE_REG_DIG_RCK_01_VALUE);
CONSYS_REG_WRITE(CONSYS_AFE_REG_WBG_PLL_02, CONSYS_AFE_REG_WBG_PLL_02_VALUE);
CONSYS_REG_WRITE(CONSYS_AFE_REG_WBG_WB_TX_01, CONSYS_AFE_REG_WBG_WB_TX_01_VALUE);
#endif
/*16.deassert CONNSYS CPU SW reset 0x10007018 "[12]=1'b0 [31:24] =8'h88 (key)" */
CONSYS_REG_WRITE(conn_reg.ap_rgu_base + CONSYS_CPU_SW_RST_OFFSET,
(CONSYS_REG_READ(conn_reg.ap_rgu_base + CONSYS_CPU_SW_RST_OFFSET) &
~CONSYS_CPU_SW_RST_BIT) | CONSYS_CPU_SW_RST_CTRL_KEY);
#else /*use HADRCODE, maybe no use.. */
/*3.assert CONNSYS CPU SW reset 0x10007018 "[12]=1'b1 [31:24]=8'h88 (key)" */
CONSYS_REG_WRITE(CONSYS_CPU_SW_RST_REG,
(CONSYS_REG_READ(CONSYS_CPU_SW_RST_REG) | CONSYS_CPU_SW_RST_BIT |
CONSYS_CPU_SW_RST_CTRL_KEY));
/*turn on SPM clock gating enable PWRON_CONFG_EN 0x10006000 32'h0b160001 */
CONSYS_REG_WRITE(CONSYS_PWRON_CONFG_EN_REG, CONSYS_PWRON_CONFG_EN_VALUE);
#if CONSYS_PWR_ON_OFF_API_AVAILABLE
#if defined(CONFIG_MTK_CLKMGR)
iRet = conn_power_on(); /* consult clkmgr owner */
if (iRet)
WMT_PLAT_ERR_FUNC("conn_power_on fail(%d)\n", iRet);
WMT_PLAT_DBG_FUNC("conn_power_on ok\n");
#else
iRet = clk_prepare_enable(clk_scp_conn_main);
if (iRet)
WMT_PLAT_ERR_FUNC("clk_prepare_enable(clk_scp_conn_main) fail(%d)\n", iRet);
WMT_PLAT_DBG_FUNC("clk_prepare_enable(clk_scp_conn_main) ok\n");
#endif /* defined(CONFIG_MTK_CLKMGR) */
#else
/*2.write conn_top1_pwr_on=1, power on conn_top1 0x10006280 [2] 1'b1 */
CONSYS_REG_WRITE(CONSYS_TOP1_PWR_CTRL_REG,
CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG) | CONSYS_SPM_PWR_ON_BIT);
/*3.read conn_top1_pwr_on_ack =1, power on ack ready 0x1000660C [1] */
while (0 == (CONSYS_PWR_ON_ACK_BIT & CONSYS_REG_READ(CONSYS_PWR_CONN_ACK_REG)))
NULL;
/*5.write conn_top1_pwr_on_s=1, power on conn_top1 0x10006280 [3] 1'b1 */
CONSYS_REG_WRITE(CONSYS_TOP1_PWR_CTRL_REG,
CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG) | CONSYS_SPM_PWR_ON_S_BIT);
/*6.write conn_clk_dis=0, enable connsys clock 0x10006280 [4] 1'b0 */
CONSYS_REG_WRITE(CONSYS_TOP1_PWR_CTRL_REG,
CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG) & ~CONSYS_CLK_CTRL_BIT);
/*7.wait 1us */
udelay(1);
/*8.read conn_top1_pwr_on_ack_s =1, power on ack ready 0x10006610 [1] */
while (0 == (CONSYS_PWR_CONN_ACK_S_BIT & CONSYS_REG_READ(CONSYS_PWR_CONN_ACK_S_REG)))
NULL;
/*9.release connsys ISO, conn_top1_iso_en=0 0x10006280 [1] 1'b0 */
CONSYS_REG_WRITE(CONSYS_TOP1_PWR_CTRL_REG,
CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG) & ~CONSYS_SPM_PWR_ISO_S_BIT);
/*10.release SW reset of connsys, conn_ap_sw_rst_b=1 0x10006280[0] 1'b1 */
CONSYS_REG_WRITE(CONSYS_TOP1_PWR_CTRL_REG,
CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG) | CONSYS_SPM_PWR_RST_BIT);
/*disable AXI BUS protect */
CONSYS_REG_WRITE(CONSYS_TOPAXI_PROT_EN, CONSYS_REG_READ(CONSYS_TOPAXI_PROT_EN) & ~CONSYS_PROT_MASK);
while (CONSYS_REG_READ(CONSYS_TOPAXI_PROT_STA1) & CONSYS_PROT_MASK)
NULL;
#endif
/*11.26M is ready now, delay 10us for mem_pd de-assert */
udelay(10);
/*enable AP bus clock : connmcu_bus_pd API: enable_clock() ++?? */
#if CONSYS_AHB_CLK_MAGEMENT
#if defined(CONFIG_MTK_CLKMGR)
enable_clock(MT_CG_INFRA_CONNMCU_BUS, "WCN_MOD");
WMT_PLAT_DBG_FUNC("enable MT_CG_INFRA_CONNMCU_BUS CLK\n");
#else
iRet = clk_prepare_enable(clk_infra_conn_main);
if (iRet)
WMT_PLAT_ERR_FUNC("clk_prepare_enable(clk_infra_conn_main) fail(%d)\n", iRet);
WMT_PLAT_DBG_FUNC("[CCF]enable clk_infra_conn_main\n");
#endif /* defined(CONFIG_MTK_CLKMGR) */
#endif
/*12.poll CONNSYS CHIP ID until 6752 is returned 0x18070008 32'h6752 */
while (retry-- > 0) {
WMT_PLAT_DBG_FUNC("CONSYS_CHIP_ID_REG(0x%08x)", CONSYS_REG_READ(CONSYS_CHIP_ID_REG));
consysHwChipId = CONSYS_REG_READ(CONSYS_CHIP_ID_REG);
if ((consysHwChipId == 0x0321) || (consysHwChipId == 0x0335) || (consysHwChipId == 0x0337)) {
WMT_PLAT_INFO_FUNC("retry(%d)consys chipId(0x%08x)\n", retry, consysHwChipId);
break;
}
msleep(20);
}
if ((0 == retry) || (0 == consysHwChipId)) {
WMT_PLAT_ERR_FUNC("Maybe has a consys power on issue,(0x%08x)\n", consysHwChipId);
WMT_PLAT_INFO_FUNC("reg dump:CONSYS_CPU_SW_RST_REG(0x%x)\n",
CONSYS_REG_READ(CONSYS_CPU_SW_RST_REG));
WMT_PLAT_INFO_FUNC("reg dump:CONSYS_PWR_CONN_ACK_REG(0x%x)\n",
CONSYS_REG_READ(CONSYS_PWR_CONN_ACK_REG));
WMT_PLAT_INFO_FUNC("reg dump:CONSYS_PWR_CONN_ACK_S_REG(0x%x)\n",
CONSYS_REG_READ(CONSYS_PWR_CONN_ACK_S_REG));
WMT_PLAT_INFO_FUNC("reg dump:CONSYS_TOP1_PWR_CTRL_REG(0x%x)\n",
CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG));
}
/*13.{default no need}update ROMDEL/PATCH RAM DELSEL if needed 0x18070114 */
/*
*14.write 1 to conn_mcu_confg ACR[1] if real speed MBIST
*(default write "1") ACR 0x18070110[18] 1'b1
*if this bit is 0, HW will do memory auto test under low CPU frequence (26M Hz)
*if this bit is 0, HW will do memory auto test under high CPU frequence(138M Hz)
*inclulding low CPU frequence
*/
CONSYS_REG_WRITE(CONSYS_MCU_CFG_ACR_REG,
CONSYS_REG_READ(CONSYS_MCU_CFG_ACR_REG) | CONSYS_MCU_CFG_ACR_MBIST_BIT);
/*update ANA_WBG(AFE) CR. AFE setting file: AP Offset = 0x180B2000 */
#if 0
/*15.default no need,update ANA_WBG(AFE) CR if needed, CONSYS_AFE_REG */
CONSYS_REG_WRITE(CONSYS_AFE_REG_DIG_RCK_01, CONSYS_AFE_REG_DIG_RCK_01_VALUE);
CONSYS_REG_WRITE(CONSYS_AFE_REG_WBG_PLL_02, CONSYS_AFE_REG_WBG_PLL_02_VALUE);
CONSYS_REG_WRITE(CONSYS_AFE_REG_WBG_WB_TX_01, CONSYS_AFE_REG_WBG_WB_TX_01_VALUE);
#endif
/*16.deassert CONNSYS CPU SW reset 0x10007018 "[12]=1'b0 [31:24] =8'h88(key)" */
CONSYS_REG_WRITE(CONSYS_CPU_SW_RST_REG,
(CONSYS_REG_READ(CONSYS_CPU_SW_RST_REG) & ~CONSYS_CPU_SW_RST_BIT) |
CONSYS_CPU_SW_RST_CTRL_KEY);
#endif
msleep(20); /* msleep < 20ms can sleep for up to 20ms */
} else {
#ifdef CONFIG_OF
#if CONSYS_AHB_CLK_MAGEMENT
#if defined(CONFIG_MTK_CLKMGR)
disable_clock(MT_CG_INFRA_CONNMCU_BUS, "WMT_MOD");
#else
clk_disable_unprepare(clk_infra_conn_main);
WMT_PLAT_DBG_FUNC("[CCF] clk_disable_unprepare(clk_infra_conn_main) calling\n");
#endif /* defined(CONFIG_MTK_CLKMGR) */
#endif
#if CONSYS_PWR_ON_OFF_API_AVAILABLE
#if defined(CONFIG_MTK_CLKMGR)
/*power off connsys by API (MT6582, MT6572 are different) API: conn_power_off() */
iRet = conn_power_off(); /* consult clkmgr owner */
if (iRet)
WMT_PLAT_ERR_FUNC("conn_power_off fail(%d)\n", iRet);
WMT_PLAT_DBG_FUNC("conn_power_off ok\n");
#else
clk_disable_unprepare(clk_scp_conn_main);
WMT_PLAT_DBG_FUNC("clk_disable_unprepare(clk_scp_conn_main) calling\n");
#endif /* defined(CONFIG_MTK_CLKMGR) */
#else
{
INT32 count = 0;
CONSYS_REG_WRITE(conn_reg.topckgen_base + CONSYS_TOPAXI_PROT_EN_OFFSET,
CONSYS_REG_READ(conn_reg.topckgen_base + CONSYS_TOPAXI_PROT_EN_OFFSET) |
CONSYS_PROT_MASK);
while ((CONSYS_REG_READ(conn_reg.topckgen_base + CONSYS_TOPAXI_PROT_STA1_OFFSET) &
CONSYS_PROT_MASK) != CONSYS_PROT_MASK) {
count++;
if (count > 1000)
break;
}
}
/*release connsys ISO, conn_top1_iso_en=1 0x10006280 [1] 1'b1 */
CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET,
CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) |
CONSYS_SPM_PWR_ISO_S_BIT);
/*assert SW reset of connsys, conn_ap_sw_rst_b=0 0x10006280[0] 1'b0 */
CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET,
CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) &
~CONSYS_SPM_PWR_RST_BIT);
/*write conn_clk_dis=1, disable connsys clock 0x10006280 [4] 1'b1 */
CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET,
CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) |
CONSYS_CLK_CTRL_BIT);
/*wait 1us */
udelay(1);
/*write conn_top1_pwr_on=0, power off conn_top1 0x10006280 [3:2] 2'b00 */
CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET,
CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) &
~(CONSYS_SPM_PWR_ON_BIT | CONSYS_SPM_PWR_ON_S_BIT));
#endif
#else
#if CONSYS_PWR_ON_OFF_API_AVAILABLE
#if CONSYS_AHB_CLK_MAGEMENT
#if defined(CONFIG_MTK_CLKMGR)
disable_clock(MT_CG_INFRA_CONNMCU_BUS, "WMT_MOD");
#else
clk_disable_unprepare(clk_infra_conn_main);
#endif /* defined(CONFIG_MTK_CLKMGR) */
#endif
#if defined(CONFIG_MTK_CLKMGR)
/*power off connsys by API: conn_power_off() */
iRet = conn_power_off(); /* consult clkmgr owner */
if (iRet)
WMT_PLAT_ERR_FUNC("conn_power_off fail(%d)\n", iRet);
WMT_PLAT_DBG_FUNC("conn_power_off ok\n");
#else
clk_disable_unprepare(clk_scp_conn_main);
WMT_PLAT_DBG_FUNC("clk_disable_unprepare(clk_scp_conn_main) calling\n");
#endif /* defined(CONFIG_MTK_CLKMGR) */
#else
{
INT32 count = 0;
CONSYS_REG_WRITE(CONSYS_TOPAXI_PROT_EN,
CONSYS_REG_READ(CONSYS_TOPAXI_PROT_EN) | CONSYS_PROT_MASK);
while ((CONSYS_REG_READ(CONSYS_TOPAXI_PROT_STA1) & CONSYS_PROT_MASK) != CONSYS_PROT_MASK) {
count++;
if (count > 1000)
break;
}
}
/*release connsys ISO, conn_top1_iso_en=1 0x10006280 [1] 1'b1 */
CONSYS_REG_WRITE(CONSYS_TOP1_PWR_CTRL_REG,
CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG) | CONSYS_SPM_PWR_ISO_S_BIT);
/*assert SW reset of connsys, conn_ap_sw_rst_b=0 0x10006280[0] 1'b0 */
CONSYS_REG_WRITE(CONSYS_TOP1_PWR_CTRL_REG,
CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG) & ~CONSYS_SPM_PWR_RST_BIT);
/*write conn_clk_dis=1, disable connsys clock 0x10006280 [4] 1'b1 */
CONSYS_REG_WRITE(CONSYS_TOP1_PWR_CTRL_REG,
CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG) | CONSYS_CLK_CTRL_BIT);
/*wait 1us */
udelay(1);
/*write conn_top1_pwr_on=0, power off conn_top1 0x10006280 [3:2] 2'b00 */
CONSYS_REG_WRITE(CONSYS_TOP1_PWR_CTRL_REG, CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG) &
~(CONSYS_SPM_PWR_ON_BIT | CONSYS_SPM_PWR_ON_S_BIT));
#endif
#endif
#if CONSYS_PMIC_CTRL_ENABLE
if (co_clock_type) {
/*VCN28 has been turned off by GPS OR FM */
#if CONSYS_CLOCK_BUF_CTRL
clk_buf_ctrl(CLK_BUF_CONN, 0);
#endif
} else {
pmic_set_register_value(PMIC_RG_VCN28_ON_CTRL, 0);
/*turn off VCN28 LDO (with PMIC_WRAP API)" */
#if defined(CONFIG_MTK_PMIC_LEGACY)
hwPowerDown(MT6328_POWER_LDO_VCN28, "wcn_drv");
#else
if (reg_VCN28) {
if (regulator_disable(reg_VCN28))
WMT_PLAT_ERR_FUNC("disable VCN_2V8 fail!\n");
else
WMT_PLAT_DBG_FUNC("disable VCN_2V8 ok\n");
}
#endif
}
/*AP power off MT6625L VCN_1V8 LDO */
pmic_set_register_value(PMIC_RG_VCN18_ON_CTRL, 0);
#if defined(CONFIG_MTK_PMIC_LEGACY)
hwPowerDown(MT6328_POWER_LDO_VCN18, "wcn_drv");
#else
if (reg_VCN18) {
if (regulator_disable(reg_VCN18))
WMT_PLAT_ERR_FUNC("disable VCN_1V8 fail!\n");
else
WMT_PLAT_DBG_FUNC("disable VCN_1V8 ok\n");
}
#endif
#endif
}
WMT_PLAT_WARN_FUNC("CONSYS-HW-REG-CTRL(0x%08x),finish\n", on);
return 0;
}
void spm_i2c_control(u32 channel, bool onoff)
{
return;
#if 0
//static int pdn = 0;
static bool i2c_onoff = 0;
#ifdef CONFIG_OF
void __iomem *base;
#else
u32 base;//, i2c_clk;
#endif
switch(channel)
{
case 0:
base = SPM_I2C0_BASE;
//i2c_clk = MT_CG_INFRA_I2C0;
break;
case 1:
base = SPM_I2C1_BASE;
//i2c_clk = MT_CG_INFRA_I2C1;
break;
case 2:
base = SPM_I2C2_BASE;
//i2c_clk = MT_CG_INFRA_I2C2;
break;
default:
base = SPM_I2C2_BASE;
break;
}
if ((1 == onoff) && (0 == i2c_onoff))
{
i2c_onoff = 1;
#if 0
#if 1
pdn = spm_read(INFRA_PDN_STA0) & (1U << i2c_clk);
spm_write(INFRA_PDN_CLR0, pdn); /* power on I2C */
#else
pdn = clock_is_on(i2c_clk);
if (!pdn)
enable_clock(i2c_clk, "spm_i2c");
#endif
#endif
spm_write(base + OFFSET_CONTROL, 0x0); /* init I2C_CONTROL */
spm_write(base + OFFSET_TRANSAC_LEN, 0x1); /* init I2C_TRANSAC_LEN */
spm_write(base + OFFSET_EXT_CONF, 0x0); /* init I2C_EXT_CONF */
spm_write(base + OFFSET_IO_CONFIG, 0x0); /* init I2C_IO_CONFIG */
spm_write(base + OFFSET_HS, 0x102); /* init I2C_HS */
}
else
if ((0 == onoff) && (1 == i2c_onoff))
{
i2c_onoff = 0;
#if 0
#if 1
spm_write(INFRA_PDN_SET0, pdn); /* restore I2C power */
#else
if (!pdn)
disable_clock(i2c_clk, "spm_i2c");
#endif
#endif
}
else
ASSERT(1);
#endif
}
static int mt_i2c_enable_dma_clk(struct mt_i2c_data *i2c, bool enable)
{
return enable ?
enable_clock(MT_CG_PERI_AP_DMA_PDN, "i2c") :
disable_clock(MT_CG_PERI_AP_DMA_PDN, "i2c");
}
/*****************************************************************************
* FUNCTION
* hal_btif_clk_ctrl
* DESCRIPTION
* control clock output enable/disable of BTIF module
* PARAMETERS
* p_base [IN] BTIF module's base address
* RETURNS
* 0 means success, negative means fail
*****************************************************************************/
int hal_btif_clk_ctrl(P_MTK_BTIF_INFO_STR p_btif, ENUM_CLOCK_CTRL flag)
{
/*In MTK BTIF, there's only one global CG on AP_DMA, no sub channel's CG bit*/
/*according to Artis's comment, clock of DMA and BTIF is default off, so we assume it to be off by default*/
int i_ret = 0;
unsigned long irq_flag = 0;
#if MTK_BTIF_ENABLE_CLK_REF_COUNTER
static atomic_t s_clk_ref = ATOMIC_INIT(0);
#else
static ENUM_CLOCK_CTRL status = CLK_OUT_DISABLE;
#endif
spin_lock_irqsave(&(g_clk_cg_spinlock), irq_flag);
#if MTK_BTIF_ENABLE_CLK_CTL
#if MTK_BTIF_ENABLE_CLK_REF_COUNTER
if (CLK_OUT_ENABLE == flag) {
if (1 == atomic_inc_return(&s_clk_ref)) {
i_ret = enable_clock(MTK_BTIF_CG_BIT, BTIF_USER_ID);
if (i_ret) {
BTIF_WARN_FUNC
("enable_clock for MTK_BTIF_CG_BIT failed, ret:%d",
i_ret);
}
}
} else if (CLK_OUT_DISABLE == flag) {
if (0 == atomic_dec_return(&s_clk_ref)) {
i_ret = disable_clock(MTK_BTIF_CG_BIT, BTIF_USER_ID);
if (i_ret) {
BTIF_WARN_FUNC
("disable_clock for MTK_BTIF_CG_BIT failed, ret:%d",
i_ret);
}
}
} else {
i_ret = ERR_INVALID_PAR;
BTIF_ERR_FUNC("invalid clock ctrl flag (%d)\n", flag);
}
#else
if (status == flag) {
i_ret = 0;
BTIF_DBG_FUNC("btif clock already %s\n",
CLK_OUT_ENABLE ==
status ? "enabled" : "disabled");
} else {
if (CLK_OUT_ENABLE == flag) {
i_ret = enable_clock(MTK_BTIF_CG_BIT, BTIF_USER_ID);
status = (0 == i_ret) ? flag : status;
if (i_ret) {
BTIF_WARN_FUNC
("enable_clock for MTK_BTIF_CG_BIT failed, ret:%d",
i_ret);
}
} else if (CLK_OUT_DISABLE == flag) {
i_ret = disable_clock(MTK_BTIF_CG_BIT, BTIF_USER_ID);
status = (0 == i_ret) ? flag : status;
if (i_ret) {
BTIF_WARN_FUNC
("disable_clock for MTK_BTIF_CG_BIT failed, ret:%d",
i_ret);
}
} else {
i_ret = ERR_INVALID_PAR;
BTIF_ERR_FUNC("invalid clock ctrl flag (%d)\n", flag);
}
}
#endif
#else
#if MTK_BTIF_ENABLE_CLK_REF_COUNTER
#else
status = flag;
#endif
i_ret = 0;
#endif
spin_unlock_irqrestore(&(g_clk_cg_spinlock), irq_flag);
#if MTK_BTIF_ENABLE_CLK_REF_COUNTER
if (0 == i_ret) {
BTIF_DBG_FUNC("btif clock %s\n",
CLK_OUT_ENABLE == flag ? "enabled" : "disabled");
} else {
BTIF_ERR_FUNC("%s btif clock failed, ret(%d)\n",
CLK_OUT_ENABLE == flag ? "enable" : "disable",
i_ret);
}
#else
if (0 == i_ret) {
BTIF_DBG_FUNC("btif clock %s\n",
CLK_OUT_ENABLE == flag ? "enabled" : "disabled");
} else {
BTIF_ERR_FUNC("%s btif clock failed, ret(%d)\n",
CLK_OUT_ENABLE == flag ? "enable" : "disable",
i_ret);
}
#endif
#if MTK_BTIF_ENABLE_CLK_CTL
BTIF_DBG_FUNC("BTIF's clock is %s\n",
(0 == clock_is_on(MTK_BTIF_CG_BIT)) ? "off" : "on");
#endif
return i_ret;
}
PVRSRV_ERROR EnableSGXClocks(SYS_DATA *psSysData)
{
#if !defined(NO_HARDWARE)
SYS_SPECIFIC_DATA *psSysSpecData = (SYS_SPECIFIC_DATA *) psSysData->pvSysSpecificData;
if (atomic_read(&psSysSpecData->sSGXClocksEnabled) != 0)
{
return PVRSRV_OK;
}
PVR_DPF((PVR_DBG_MESSAGE, "EnableSGXClocks: Enabling SGX Clocks"));
#if defined(LDM_PLATFORM) && !defined(PVR_DRI_DRM_NOT_PCI) && defined(CONFIG_PM_RUNTIME)
{
int res = pm_runtime_get_sync(&gpsPVRLDMDev->dev);
if (res < 0)
{
PVR_DPF((PVR_DBG_ERROR, "EnableSGXClocks: pm_runtime_get_sync failed (%d)", -res));
return PVRSRV_ERROR_UNABLE_TO_ENABLE_CLOCK;
}
}
#endif
//disable_clock(MT65XX_PDN_MM_MFG_HALF, "MFG");
//disable_clock(MT65XX_PDN_MM_MFG, "MFG");
//disable_clock(MT65XX_PDN_MM_G3D, "MFG");
#if USE_SYS_CLOCK
#if !defined(MTK_CLK_CTRL)
DRV_WriteReg16(PLL_CON11, DRV_Reg16(PLL_CON11)|0x0C00); // F3D_CK_SEL
#endif
DRV_WriteReg32(MMSYS2_CONFG_BASE + 0x0504, 0x4); // MFG_CORE_CK_SEL DCM
#else
#if !defined(MTK_CLK_CTRL)
DRV_WriteReg16(PLL_CON11, DRV_Reg16(PLL_CON11)|0x0C00); // F3D_CK_SEL
#endif
DRV_WriteReg32(MMSYS2_CONFG_BASE + 0x0504, 0x6); // MFG_CORE_CK_SEL DCM
#endif
//DRV_WriteReg32(MMSYS2_CONFG_BASE+0x400, DRV_Reg32(MMSYS2_CONFG_BASE+0x400)|0x4);
enable_clock(MT65XX_PDN_MM_G3D, "MFG");
enable_clock(MT65XX_PDN_MM_MFG, "MFG");
enable_clock(MT65XX_PDN_MM_MFG_HALF, "MFG");
DRV_WriteReg32(MMSYS2_CONFG_BASE+0x400, DRV_Reg32(MMSYS2_CONFG_BASE+0x400)|0x4);
#if defined(MTK_USE_GDC)
SysInitGDC();
#endif
#if 0
DRV_WriteReg16(0xF0007404, 0x6);
DRV_WriteReg16(0xF0007400, 0x4800);
DRV_WriteReg16(0xF0007400, 0x0800);
DRV_WriteReg16(0xF0007400, 0x8800);
while(DRV_Reg16(0xF0007404) & 0x8000){}
PVRSRVReleasePrintf("MainPLL: 0x%x", DRV_Reg16(0xF0007410));
DRV_WriteReg16(0xF0007404, 0x15);
DRV_WriteReg16(0xF0007400, 0x4800);
DRV_WriteReg16(0xF0007400, 0x0800);
DRV_WriteReg16(0xF0007400, 0x8800);
while(DRV_Reg16(0xF0007404) & 0x8000){}
PVRSRVReleasePrintf("MEMPLL: 0x%x", DRV_Reg16(0xF0007410));
#endif
SysEnableSGXInterrupts(psSysData);
atomic_set(&psSysSpecData->sSGXClocksEnabled, 1);
#else
PVR_UNREFERENCED_PARAMETER(psSysData);
#endif
return PVRSRV_OK;
}
int IMM_auxadc_GetOneChannelValue(int dwChannel, int data[4], int* rawdata)
{
unsigned int channel[16] = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
int idle_count =0;
int data_ready_count=0;
mutex_lock(&mutex_get_cali_value);
#if 0
if(enable_clock(MT_PDN_PERI_AUXADC,"AUXADC"))
{
printk("hwEnableClock AUXADC failed.");
}
#endif
if(dwChannel == PAD_AUX_XP)mt_auxadc_disable_penirq();
//step1 check con2 if auxadc is busy
while ((*(volatile u16 *)AUXADC_CON2) & 0x01)
{
printk("[adc_api]: wait for module idle\n");
msleep(100);
idle_count++;
if(idle_count>30)
{
//wait for idle time out
printk("[adc_api]: wait for auxadc idle time out\n");
mutex_unlock(&mutex_get_cali_value);
return -1;
}
}
// step2 clear bit
if(0 == adc_auto_set)
{
//clear bit
AUXADC_DRV_ClearBits16((volatile u16 *)AUXADC_CON1, (1 << dwChannel));
}
//step3 read channle and make sure old ready bit ==0
while ((*(volatile u16 *)(AUXADC_DAT0 + dwChannel * 0x04)) & (1<<12))
{
printk("[adc_api]: wait for channel[%d] ready bit clear\n",dwChannel);
msleep(10);
data_ready_count++;
if(data_ready_count>30)
{
//wait for idle time out
printk("[adc_api]: wait for channel[%d] ready bit clear time out\n",dwChannel);
mutex_unlock(&mutex_get_cali_value);
return -2;
}
}
//step4 set bit to trigger sample
if(0==adc_auto_set)
{
AUXADC_DRV_SetBits16((volatile u16 *)AUXADC_CON1, (1 << dwChannel));
}
//step5 read channle and make sure ready bit ==1
udelay(25);//we must dealay here for hw sample cahnnel data
while (0==((*(volatile u16 *)(AUXADC_DAT0 + dwChannel * 0x04)) & (1<<12)))
{
printk("[adc_api]: wait for channel[%d] ready bit ==1\n",dwChannel);
msleep(10);
data_ready_count++;
if(data_ready_count>30)
{
//wait for idle time out
printk("[adc_api]: wait for channel[%d] data ready time out\n",dwChannel);
mutex_unlock(&mutex_get_cali_value);
return -3;
}
}
//step6 read data
channel[dwChannel] = (*(volatile u16 *)(AUXADC_DAT0 + dwChannel * 0x04)) & 0x0FFF;
if(NULL != rawdata)
{
*rawdata = channel[dwChannel];
}
//printk("[adc_api: imm mode raw data => channel[%d] = %d\n",dwChannel, channel[dwChannel]);
//printk("[adc_api]: imm mode => channel[%d] = %d.%02d\n", dwChannel, (channel[dwChannel] * 150 / AUXADC_PRECISE / 100), ((channel[dwChannel] * 150 / AUXADC_PRECISE) % 100));
data[0] = (channel[dwChannel] * 150 / AUXADC_PRECISE / 100);
data[1] = ((channel[dwChannel] * 150 / AUXADC_PRECISE) % 100);
#if 0
if(disable_clock(MT_PDN_PERI_AUXADC,"AUXADC"))
{
printk("hwEnableClock AUXADC failed.");
}
#endif
mutex_unlock(&mutex_get_cali_value);
return 0;
}
static int ufoe_init(DISP_MODULE_ENUM module,void * handle)
{
enable_clock(MT_CG_DISP0_DISP_UFOE, "ufoe");
DDPMSG("ufoe_clock on CG 0x%x \n", DISP_REG_GET(DISP_REG_CONFIG_MMSYS_CG_CON0));
return 0;
}
static int simple_sd_ioctl_set_driving(struct msdc_ioctl* msdc_ctl)
{
u32 base;
struct msdc_host *host;
#if DEBUG_MMC_IOCTL
unsigned int l_value;
#endif
if (msdc_ctl->host_num == 0){
#ifndef CFG_DEV_MSDC0
printk("host%d is not config\n", msdc_ctl->host_num);
return -1;
#endif
} else if (msdc_ctl->host_num == 1) {
#ifndef CFG_DEV_MSDC1
printk("host%d is not config\n", msdc_ctl->host_num);
return -1;
#endif
} else if (msdc_ctl->host_num == 2) {
#ifndef CFG_DEV_MSDC2
printk("host%d is not config\n", msdc_ctl->host_num);
return -1;
#endif
} else if (msdc_ctl->host_num == 3) {
#ifndef CFG_DEV_MSDC3
printk("host%d is not config\n", msdc_ctl->host_num);
return -1;
#endif
} else if (msdc_ctl->host_num == 4) {
#ifndef CFG_DEV_MSDC4
printk("host%d is not config\n", msdc_ctl->host_num);
return -1;
#endif
}
base = mtk_msdc_host[msdc_ctl->host_num]->base;
#ifndef FPGA_PLATFORM
enable_clock(15 + mtk_msdc_host[msdc_ctl->host_num]->id, "SD");
#endif
#if DEBUG_MMC_IOCTL
//printk("set: clk pull down driving is 0x%x\n", msdc_ctl->clk_pd_driving);
printk("set: clk driving is 0x%x\n", msdc_ctl->clk_pu_driving);
//printk("set: cmd pull down driving is 0x%x\n", msdc_ctl->cmd_pd_driving);
printk("set: cmd driving is 0x%x\n", msdc_ctl->cmd_pu_driving);
//printk("set: dat pull down driving is 0x%x\n", msdc_ctl->dat_pd_driving);
printk("set: dat driving is 0x%x\n", msdc_ctl->dat_pu_driving);
#endif
#ifdef FPGA_PLATFORM
sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKDRVN, msdc_ctl->clk_pd_driving);
sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKDRVP, msdc_ctl->clk_pu_driving);
sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDDRVN, msdc_ctl->cmd_pd_driving);
sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDDRVP, msdc_ctl->cmd_pu_driving);
sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATDRVN, msdc_ctl->dat_pd_driving);
sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATDRVP, msdc_ctl->dat_pu_driving);
#else
host = mtk_msdc_host[msdc_ctl->host_num];
host->hw->clk_drv = msdc_ctl->clk_pu_driving;
host->hw->cmd_drv = msdc_ctl->cmd_pu_driving;
host->hw->dat_drv = msdc_ctl->dat_pu_driving;
host->hw->clk_drv_sd_18 = msdc_ctl->clk_pu_driving;
host->hw->cmd_drv_sd_18 = msdc_ctl->cmd_pu_driving;
host->hw->dat_drv_sd_18 = msdc_ctl->dat_pu_driving;
msdc_set_driving(host,host->hw,0);
#endif
#if DEBUG_MMC_IOCTL
l_value = 0;
//sdr_get_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKDRVN, l_value);
//printk("read: clk pull down driving is 0x%x\n", l_value);
l_value = (msdc_dump_padctl0(msdc_ctl->host_num) & 0x7);
//sdr_get_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKDRVP, l_value);
printk("read: clk driving is 0x%x\n", l_value);
l_value = (msdc_dump_padctl1(msdc_ctl->host_num) & 0x7);;
//sdr_get_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDDRVN, l_value);
printk("read: cmd driving is 0x%x\n", l_value);
//l_value = 0;
//sdr_get_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDDRVP, l_value);
//printk("read: cmd pull up driving is 0x%x\n", l_value);
l_value = (msdc_dump_padctl2(msdc_ctl->host_num) & 0x7);;
//sdr_get_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATDRVN, l_value);
printk("read: dat driving is 0x%x\n", l_value);
//l_value = 0;
//sdr_get_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATDRVP, l_value);
//printk("read: dat pull up driving is 0x%x\n", l_value);
#endif
return 0;
}
/*****************************************************************************
* FUNCTION
* hal_btif_clk_ctrl
* DESCRIPTION
* control clock output enable/disable of DMA module
* PARAMETERS
* p_dma_info [IN] pointer to BTIF dma channel's information
* RETURNS
* 0 means success, negative means fail
*****************************************************************************/
int hal_btif_dma_clk_ctrl(P_MTK_DMA_INFO_STR p_dma_info, ENUM_CLOCK_CTRL flag)
{
/*In MTK DMA BTIF channel, there's only one global CG on AP_DMA, no sub channel's CG bit*/
/*according to Artis's comment, clock of DMA and BTIF is default off, so we assume it to be off by default*/
int i_ret = 0;
unsigned long irq_flag = 0;
#if MTK_BTIF_ENABLE_CLK_REF_COUNTER
static atomic_t s_clk_ref = ATOMIC_INIT(0);
#else
static ENUM_CLOCK_CTRL status = CLK_OUT_DISABLE;
#endif
#if defined(CONFIG_MTK_LEGACY)
spin_lock_irqsave(&(g_clk_cg_spinlock), irq_flag);
#endif
#if MTK_BTIF_ENABLE_CLK_CTL
#if MTK_BTIF_ENABLE_CLK_REF_COUNTER
if (CLK_OUT_ENABLE == flag) {
if (1 == atomic_inc_return(&s_clk_ref)) {
#if defined(CONFIG_MTK_LEGACY)
i_ret =
enable_clock(MTK_BTIF_APDMA_CLK_CG, DMA_USER_ID);
if (i_ret) {
BTIF_WARN_FUNC
("enable_clock for MTK_BTIF_APDMA_CLK_CG failed, ret:%d",
i_ret);
}
#else
clk_prepare(clk_btif_apdma);
spin_lock_irqsave(&(g_clk_cg_spinlock), irq_flag);
clk_enable(clk_btif_apdma);
spin_unlock_irqrestore(&(g_clk_cg_spinlock), irq_flag);
BTIF_INFO_FUNC("[CCF]enable clk_btif_apdma\n");
#endif /* defined(CONFIG_MTK_LEGACY) */
}
} else if (CLK_OUT_DISABLE == flag) {
if (0 == atomic_dec_return(&s_clk_ref)) {
#if defined(CONFIG_MTK_LEGACY)
i_ret =
disable_clock(MTK_BTIF_APDMA_CLK_CG, DMA_USER_ID);
if (i_ret) {
BTIF_WARN_FUNC
("disable_clock for MTK_BTIF_APDMA_CLK_CG failed, ret:%d",
i_ret);
}
#else
spin_lock_irqsave(&(g_clk_cg_spinlock), irq_flag);
clk_disable(clk_btif_apdma);
spin_unlock_irqrestore(&(g_clk_cg_spinlock), irq_flag);
clk_unprepare(clk_btif_apdma);
BTIF_INFO_FUNC("[CCF] clk_disable_unprepare(clk_btif_apdma) calling\n");
#endif /* defined(CONFIG_MTK_LEGACY) */
}
} else {
i_ret = ERR_INVALID_PAR;
BTIF_ERR_FUNC("invalid clock ctrl flag (%d)\n", flag);
}
#else
if (status == flag) {
i_ret = 0;
BTIF_DBG_FUNC("dma clock already %s\n",
CLK_OUT_ENABLE ==
status ? "enabled" : "disabled");
} else {
if (CLK_OUT_ENABLE == flag) {
#if defined(CONFIG_MTK_LEGACY)
i_ret =
enable_clock(MTK_BTIF_APDMA_CLK_CG, DMA_USER_ID);
status = (0 == i_ret) ? flag : status;
if (i_ret) {
BTIF_WARN_FUNC
("enable_clock for MTK_BTIF_APDMA_CLK_CG failed, ret:%d",
i_ret);
}
#else
clk_prepare(clk_btif_apdma);
spin_lock_irqsave(&(g_clk_cg_spinlock), irq_flag);
clk_enable(clk_btif_apdma);
spin_unlock_irqrestore(&(g_clk_cg_spinlock), irq_flag);
BTIF_INFO_FUNC("[CCF]enable clk_btif_apdma\n");
#endif /* defined(CONFIG_MTK_LEGACY) */
} else if (CLK_OUT_DISABLE == flag) {
#if defined(CONFIG_MTK_LEGACY)
i_ret =
disable_clock(MTK_BTIF_APDMA_CLK_CG, DMA_USER_ID);
status = (0 == i_ret) ? flag : status;
if (i_ret) {
BTIF_WARN_FUNC
("disable_clock for MTK_BTIF_APDMA_CLK_CG failed, ret:%d",
i_ret);
}
#else
spin_lock_irqsave(&(g_clk_cg_spinlock), irq_flag);
clk_disable(clk_btif_apdma);
spin_unlock_irqrestore(&(g_clk_cg_spinlock), irq_flag);
clk_unprepare(clk_btif_apdma);
BTIF_INFO_FUNC("[CCF] clk_disable_unprepare(clk_btif_apdma) calling\n");
#endif /* defined(CONFIG_MTK_LEGACY) */
} else {
i_ret = ERR_INVALID_PAR;
BTIF_ERR_FUNC("invalid clock ctrl flag (%d)\n", flag);
}
}
#endif
#else
#if MTK_BTIF_ENABLE_CLK_REF_COUNTER
#else
status = flag;
#endif
i_ret = 0;
#endif
#if defined(CONFIG_MTK_LEGACY)
spin_unlock_irqrestore(&(g_clk_cg_spinlock), irq_flag);
#endif
#if MTK_BTIF_ENABLE_CLK_REF_COUNTER
if (0 == i_ret) {
BTIF_DBG_FUNC("dma clock %s\n",
CLK_OUT_ENABLE == flag ? "enabled" : "disabled");
} else {
BTIF_ERR_FUNC("%s dma clock failed, ret(%d)\n",
CLK_OUT_ENABLE == flag ? "enable" : "disable",
i_ret);
}
#else
if (0 == i_ret) {
BTIF_DBG_FUNC("dma clock %s\n",
CLK_OUT_ENABLE == flag ? "enabled" : "disabled");
} else {
BTIF_ERR_FUNC("%s dma clock failed, ret(%d)\n",
CLK_OUT_ENABLE == flag ? "enable" : "disable",
i_ret);
}
#endif
#if defined(CONFIG_MTK_LEGACY)
BTIF_DBG_FUNC("DMA's clock is %s\n",
(0 == clock_is_on(MTK_BTIF_APDMA_CLK_CG)) ? "off" : "on");
#endif
return i_ret;
}
int mali_platform_power_mode_change(mali_power_mode power_mode)
{
unsigned long flags;
switch (power_mode)
{
case MALI_POWER_MODE_ON:
MALI_DEBUG_PRINT(3, ("Mali platform: Got MALI_POWER_MODE_ON event, %s\n",
atomic_read((atomic_t *)&bPoweroff) ? "powering on" : "already on"));
if (atomic_read((atomic_t *)&bPoweroff) == 1)
{
MALI_DEBUG_PRINT(2,("[+]MFG enable_clock \n"));
mfg_pwr_lock(flags);
if (!clock_is_on(MT_CG_MFG_PDN_BG3D_SW_CG))
{
enable_clock(MT_CG_MFG_PDN_BG3D_SW_CG, "G3D_DRV");
/// enable WHPLL and set the GPU freq. to 500MHz
if(get_gpu_level() != GPU_LEVEL_0){
clkmux_sel(MT_CLKMUX_MFG_MUX_SEL, MT_CG_GPU_500P5M_EN, "G3D_DRV");
}
}
mfg_pwr_unlock(flags);
MALI_DEBUG_PRINT(2,("[-]MFG enable_clock \n"));
#if defined(CONFIG_MALI400_PROFILING)
_mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE |
MALI_PROFILING_EVENT_CHANNEL_GPU |
MALI_PROFILING_EVENT_REASON_SINGLE_GPU_FREQ_VOLT_CHANGE, 500,
1200/1000, 0, 0, 0);
#endif
atomic_set((atomic_t *)&bPoweroff, 0);
}
break;
case MALI_POWER_MODE_LIGHT_SLEEP:
case MALI_POWER_MODE_DEEP_SLEEP:
MALI_DEBUG_PRINT(1, ("Mali platform: Got %s event, %s\n", power_mode ==
MALI_POWER_MODE_LIGHT_SLEEP ? "MALI_POWER_MODE_LIGHT_SLEEP" :
"MALI_POWER_MODE_DEEP_SLEEP", atomic_read((atomic_t *)&bPoweroff) ? "already off" : "powering off"));
if (atomic_read((atomic_t *)&bPoweroff) == 0)
{
MALI_DEBUG_PRINT(2,("[+]MFG disable_clock \n"));
mfg_pwr_lock(flags);
if (clock_is_on(MT_CG_MFG_PDN_BG3D_SW_CG))
{
disable_clock(MT_CG_MFG_PDN_BG3D_SW_CG, "G3D_DRV");
}
mfg_pwr_unlock(flags);
MALI_DEBUG_PRINT(2,("[-]MFG disable_clock \n"));
#if defined(CONFIG_MALI400_PROFILING)
_mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE |
MALI_PROFILING_EVENT_CHANNEL_GPU |
MALI_PROFILING_EVENT_REASON_SINGLE_GPU_FREQ_VOLT_CHANGE, 0, 0, 0, 0, 0);
#endif
atomic_set((atomic_t *)&bPoweroff, 1);
}
break;
}
}
static int mt_i2c_enable_clk(struct mt_i2c_data *i2c, bool enable)
{
return enable ?
enable_clock(i2c->pdn, "i2c") :
disable_clock(i2c->pdn, "i2c");
}