void start_cpu(u32 reset_vector)
{
debug("start_cpu entry, reset_vector = %x\n", reset_vector);
t114_init_clocks();
/* Enable VDD_CPU */
enable_cpu_power_rail();
/* Get the CPU(s) running */
enable_cpu_clocks();
/* Enable CoreSight */
clock_enable_coresight(1);
/* Take CPU(s) out of reset */
remove_cpu_resets();
/*
* Set the entry point for CPU execution from reset,
* if it's a non-zero value.
*/
if (reset_vector)
writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR);
/* If the CPU(s) don't already have power, power 'em up */
powerup_cpus();
}
void ccplex_cpu_prepare(void)
{
enable_cpu_clocks();
enable_cpu_power_partitions();
mainboard_configure_pmc();
mainboard_enable_vdd_cpu();
request_ram_repair();
}
void ccplex_cpu_prepare(void)
{
enable_cpu_clocks();
/*
* The POR value of CAR2PMC_CPU_ACK_WIDTH is 0x200.
* The recommended value is 0.
*/
set_cpu_ack_width(0);
enable_cpu_power_partitions();
mainboard_configure_pmc();
mainboard_enable_vdd_cpu();
request_ram_repair();
}
void start_cpu(u32 reset_vector)
{
struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
debug("%s entry, reset_vector = %x\n", __func__, reset_vector);
tegra124_init_clocks();
/* Set power-gating timer multiplier */
writel((MULT_8 << TIMER_MULT_SHIFT) | (MULT_8 << TIMER_MULT_CPU_SHIFT),
&pmc->pmc_pwrgate_timer_mult);
enable_cpu_power_rail();
powerup_cpus();
tegra124_ram_repair();
enable_cpu_clocks();
clock_enable_coresight(1);
writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR);
remove_cpu_resets();
debug("%s exit, should continue @ reset_vector\n", __func__);
}
