void enable_layerscape_ns_access(void) { #ifdef CONFIG_ARM64 if (current_el() == 3) #endif enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev)); }
int board_init(void) { #ifndef CONFIG_SYS_FSL_NO_SERDES fsl_serdes_init(); #ifndef CONFIG_QSPI_BOOT config_serdes_mux(); #endif #endif ls1021x_config_caam_stream_id(sec_liodn_tbl, ARRAY_SIZE(sec_liodn_tbl)); ls102xa_config_smmu_stream_id(dev_stream_id, ARRAY_SIZE(dev_stream_id)); #ifdef CONFIG_LS102XA_NS_ACCESS enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev)); #endif #ifdef CONFIG_U_QE u_qe_init(); #endif #ifdef CONFIG_DEEP_SLEEP ls1twr_program_regulator(); #endif return 0; }
void board_init_f(ulong dummy) { /* Clear the BSS */ memset(__bss_start, 0, __bss_end - __bss_start); get_clocks(); #if defined(CONFIG_DEEP_SLEEP) if (is_warm_boot()) fsl_dp_disable_console(); #endif preloader_console_init(); dram_init(); /* Allow OCRAM access permission as R/W */ #ifdef CONFIG_LS102XA_NS_ACCESS enable_devices_ns_access(&ns_dev[4], 1); enable_devices_ns_access(&ns_dev[7], 1); #endif board_init_r(NULL, 0); }
void enable_layerscape_ns_access(void) { enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev)); }
void board_sleep_prepare(void) { #ifdef CONFIG_LS102XA_NS_ACCESS enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev)); #endif }