static void setup_spi(void)
{
gpio_request(IMX_GPIO_NR(4, 24), "spi_cs0");
gpio_direction_output(IMX_GPIO_NR(4, 24), 1);
SETUP_IOMUX_PADS(ecspi3_pads);
enable_spi_clk(true, 2);
}
static void setup_spi(void)
{
gpio_request(IMX_GPIO_NR(3, 19), "spi_cs0");
gpio_direction_output(IMX_GPIO_NR(3, 19), 1);
imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
enable_spi_clk(true, 0);
}
static void setup_spi(void)
{
int i;
imx_iomux_v3_setup_multiple_pads(ecspi4_pads, ARRAY_SIZE(ecspi4_pads));
for (i = 0; i < 3; i++)
enable_spi_clk(true, i);
/* set cs1 to high */
gpio_direction_output(ECSPI4_CS1, 1);
}
static void setup_spi(void)
{
#ifdef CONFIG_TARGET_ZC5202
gpio_request(IMX_GPIO_NR(5, 17), "spi_cs0");
gpio_request(IMX_GPIO_NR(5, 9), "spi_cs1");
gpio_direction_output(IMX_GPIO_NR(5, 17), 1);
gpio_direction_output(IMX_GPIO_NR(5, 9), 1);
imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
#endif
gpio_request(IMX_GPIO_NR(3, 20), "spi4_cs0");
gpio_direction_output(IMX_GPIO_NR(3, 20), 1);
imx_iomux_v3_setup_multiple_pads(ecspi4_pads, ARRAY_SIZE(ecspi4_pads));
enable_spi_clk(true, 3);
}
static void setup_spi(void)
{
int i;
imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
#if (CONFIG_SYS_BOARD_VERSION == 2)
imx_iomux_v3_setup_multiple_pads(ecspi4_pads, ARRAY_SIZE(ecspi4_pads));
#endif
for (i = 0; i < 4; i++)
enable_spi_clk(true, i);
gpio_direction_output(ECSPI1_CS0, 1);
#if (CONFIG_SYS_BOARD_VERSION == 2)
gpio_direction_output(ECSPI4_CS1, 0);
/* set cs0 to high (second device on spi bus #4) */
gpio_direction_output(ECSPI4_CS0, 1);
#elif (CONFIG_SYS_BOARD_VERSION == 3)
gpio_direction_output(ECSPI1_CS1, 1);
#endif
}
static void spl_dram_init(void)
{
struct mx6_ddr_sysinfo sysinfo = {
/* width of data bus:0=16,1=32,2=64 */
.dsize = 2,
/* config for full 4GB range so that get_mem_size() works */
.cs_density = 32, /* 32Gb per CS */
/* single chip select */
.ncs = 1,
.cs1_mirror = 0,
.rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */
.rtt_nom = 2 /*DDR3_RTT_120_OHM*/, /* RTT_Nom = RZQ/2 */
.walat = 1, /* Write additional latency */
.ralat = 5, /* Read additional latency */
.mif3_mode = 3, /* Command prediction working mode */
.bi_on = 1, /* Bank interleaving enabled */
.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
.pd_fast_exit = 1, /* enable precharge power-down fast exit */
.ddr_type = DDR_TYPE_DDR3,
.refsel = 1, /* Refresh cycles at 32KHz */
.refr = 7, /* 8 refresh commands per refresh cycle */
};
mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);
mx6_dram_cfg(&sysinfo, &mx6_4x256mx16_mmdc_calib, &mt41k128m16jt_125);
#ifdef CONFIG_MX6_DDRCAL
spl_dram_perform_cal(&sysinfo);
#endif
}
#ifdef CONFIG_SPL_SPI_SUPPORT
static void displ5_init_ecspi(void)
{
displ5_set_iomux_ecspi_spl();
enable_spi_clk(1, 1);
}
static void cm_fx6_setup_ecspi(void)
{
cm_fx6_set_ecspi_iomux();
enable_spi_clk(1, 0);
}
