static void misoc_net_interrupt_work(FAR void *arg) { FAR struct misoc_net_driver_s *priv = (FAR struct misoc_net_driver_s *)arg; /* Process pending Ethernet interrupts */ net_lock(); /* Check if we received an incoming packet, if so, call misoc_net_receive() */ if (ethmac_sram_writer_ev_pending_read() & ETHMAC_EV_SRAM_WRITER) { misoc_net_receive(priv); } /* Check if a packet transmission just completed. If so, call misoc_net_txdone. * This may disable further Tx interrupts if there are no pending * transmissions. */ if (ethmac_sram_reader_ev_pending_read() & ETHMAC_EV_SRAM_READER) { misoc_net_txdone(priv); ethmac_sram_reader_ev_pending_write(1); } net_unlock(); /* Re-enable Ethernet interrupts */ up_enable_irq(ETHMAC_INTERRUPT); }
err_t liteeth_init(struct netif *netif) { int i; netif->hwaddr_len = 6; for(i=0;i<netif->hwaddr_len;i++) netif->hwaddr[i] = macadr[i]; netif->name[0] = IFNAME0; netif->name[1] = IFNAME1; netif->output = etharp_output; netif->linkoutput = liteeth_low_level_output; netif->mtu = 1500; netif->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP; ethmac_sram_reader_ev_pending_write(ETHMAC_EV_SRAM_READER); ethmac_sram_writer_ev_pending_write(ETHMAC_EV_SRAM_WRITER); rxbuffer0 = (char *)ETHMAC_RX0_BASE; rxbuffer1 = (char *)ETHMAC_RX1_BASE; txbuffer0 = (char *)ETHMAC_TX0_BASE; txbuffer1 = (char *)ETHMAC_TX1_BASE; txslot = 0; txbuffer = txbuffer0; return ERR_OK; }
static void liteeth_low_level_init(struct netif *netif) { int i; netif->hwaddr_len = 6; for(i=0;i<netif->hwaddr_len;i++) netif->hwaddr[i] = macadr[i]; netif->mtu = 1514; netif->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP; ethmac_sram_reader_ev_pending_write(ETHMAC_EV_SRAM_READER); ethmac_sram_writer_ev_pending_write(ETHMAC_EV_SRAM_WRITER); rxbuffer0 = (char *)ETHMAC_RX0_BASE; rxbuffer1 = (char *)ETHMAC_RX1_BASE; txbuffer0 = (char *)ETHMAC_TX0_BASE; txbuffer1 = (char *)ETHMAC_TX1_BASE; rxslot = 0; txslot = 0; rxbuffer = rxbuffer0; txbuffer = txbuffer0; }
int misoc_net_initialize(int intf) { FAR struct misoc_net_driver_s *priv; /* Get the interface structure associated with this interface number. */ DEBUGASSERT(intf < CONFIG_MISOC_NET_NINTERFACES); priv = &g_misoc_net[intf]; /* Check if a Ethernet chip is recognized at its I/O base */ /* Attach the IRQ to the driver */ if (irq_attach(ETHMAC_INTERRUPT, misoc_net_interrupt, NULL)) { /* We could not attach the ISR to the interrupt */ return -EAGAIN; } /* clear pending int */ ethmac_sram_writer_ev_pending_write(1); ethmac_sram_reader_ev_pending_write(1); /* Initialize the driver structure */ memset(priv, 0, sizeof(struct misoc_net_driver_s)); priv->rx0_buf = (uint8_t *)ETHMAC_RX0_BASE; priv->rx1_buf = (uint8_t *)ETHMAC_RX1_BASE; priv->tx0_buf = (uint8_t *)ETHMAC_TX0_BASE; priv->tx1_buf = (uint8_t *)ETHMAC_TX1_BASE; priv->tx_buf = priv->tx0_buf; priv->tx_slot=0; priv->misoc_net_dev.d_buf = g_pktbuf; /* Single packet buffer */ priv->misoc_net_dev.d_ifup = misoc_net_ifup; /* I/F up (new IP address) callback */ priv->misoc_net_dev.d_ifdown = misoc_net_ifdown; /* I/F down callback */ priv->misoc_net_dev.d_txavail = misoc_net_txavail; /* New TX data callback */ #ifdef CONFIG_NET_IGMP priv->misoc_net_dev.d_addmac = misoc_net_addmac; /* Add multicast MAC address */ priv->misoc_net_dev.d_rmmac = misoc_net_rmmac; /* Remove multicast MAC address */ #endif priv->misoc_net_dev.d_private = (FAR void *)g_misoc_net; /* Used to recover private state from dev */ /* Create a watchdog for timing polling for and timing of transmissions */ priv->misoc_net_txpoll = wd_create(); /* Create periodic poll timer */ priv->misoc_net_txtimeout = wd_create(); /* Create TX timeout timer */ /* Put the interface in the down state. This usually amounts to resetting * the device and/or calling misoc_net_ifdown(). */ /* Read the MAC address from the hardware into * priv->misoc_net_dev.d_mac.ether.ether_addr_octet */ /* Register the device with the OS so that socket IOCTLs can be performed */ (void)netdev_register(&priv->misoc_net_dev, NET_LL_ETHERNET); return OK; }