示例#1
0
static int exynos4_pm_suspend(void)
{
	unsigned long tmp;

	if (!exynos4_is_c2c_use())
		s3c_pm_do_save(exynos4_core_save, ARRAY_SIZE(exynos4_core_save));

	s3c_pm_do_save(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save));

	/* Setting Central Sequence Register for power down mode */

	tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
	tmp &= ~(S5P_CENTRAL_LOWPWR_CFG);
	__raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);

	/* When enter sleep mode, USE_DELAYED_RESET_ASSERTION have to disable */
	if (!soc_is_exynos4210())
		exynos4_reset_assert_ctrl(0);

	if (!soc_is_exynos4210()) {
		tmp = S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0;
		__raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);

		if (exynos4_is_c2c_use()) {
			tmp = __raw_readl(S5P_WAKEUP_MASK_COREBLK);
			tmp &= ~(1 << 20);
			__raw_writel(tmp, S5P_WAKEUP_MASK_COREBLK);
			tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION_COREBLK);
			tmp &= ~S5P_CENTRAL_SEQ_COREBLK_CONF;
			__raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION_COREBLK);
		}
	}

	return 0;
}
void exynos4_sys_powerdown_conf(enum sys_powerdown mode)
{
	unsigned int count = entry_cnt;
	unsigned int tmp;

	for (; count > 0; count--)
		__raw_writel(exynos4_pmu_config[count - 1].val[mode],
				exynos4_pmu_config[count - 1].reg);

	if ((!soc_is_exynos4210()) && (exynos4_is_c2c_use())) {
		for (count = 0 ; count < ARRAY_SIZE(exynos4x12_c2c_pmu_conf) ; count++)
			__raw_writel(exynos4x12_c2c_pmu_conf[count].val[mode],
					exynos4x12_c2c_pmu_conf[count].reg);

		if (soc_is_exynos4212())
			__raw_writel(exynos4212_c2c_pmu_conf[0].val[mode],
					exynos4212_c2c_pmu_conf[0].reg);

		for (count = 0 ; count < ARRAY_SIZE(exynos4_config_for_c2c) ; count++) {
			tmp = __raw_readl(exynos4_config_for_c2c[count].reg);
			tmp |= exynos4_config_for_c2c[count].val;
			__raw_writel(tmp, exynos4_config_for_c2c[count].reg);
		}
	}
}
static void exynos5_pm_prepare(void)
{
	unsigned int tmp;

	if (exynos5_sleep_gpio_table_set)
		exynos5_sleep_gpio_table_set();

	if (samsung_rev() < EXYNOS5250_REV_1_0) {
		/* Disable USE_RETENTION of JPEG_MEM_OPTION */
		tmp = __raw_readl(EXYNOS5_JPEG_MEM_OPTION);
		tmp &= ~EXYNOS5_OPTION_USE_RETENTION;
		__raw_writel(tmp, EXYNOS5_JPEG_MEM_OPTION);
	}

	if (samsung_rev() >= EXYNOS5250_REV_1_0) {
		tmp = __raw_readl(EXYNOS5_ARM_L2_OPTION);
		tmp &= ~(1 << 4);
		__raw_writel(tmp, EXYNOS5_ARM_L2_OPTION);
	}

	/* Set value of power down register for sleep mode */
	exynos5_sys_powerdown_conf(SYS_SLEEP);
	__raw_writel(S5P_CHECK_SLEEP, REG_INFORM1);

	/* ensure at least INFORM0 has the resume address */
	__raw_writel(virt_to_phys(s3c_cpu_resume), REG_INFORM0);

	if (exynos4_is_c2c_use()) {
		tmp = __raw_readl(EXYNOS5_INTRAM_MEM_OPTION);
		tmp &= ~EXYNOS5_OPTION_USE_RETENTION;
		__raw_writel(tmp, EXYNOS5_INTRAM_MEM_OPTION);
	}

	s3c_pm_do_restore_core(exynos5_set_clksrc, ARRAY_SIZE(exynos5_set_clksrc));
}
示例#4
0
void exynos5_sys_powerdown_conf(enum sys_powerdown mode)
{
	unsigned int count = entry_cnt;
	unsigned int i;

	exynos5_init_pmu();

	for (; count > 0; count--)
		__raw_writel(exynos5_pmu_config[count - 1].val[mode],
				exynos5_pmu_config[count - 1].reg);

	if (samsung_rev() < EXYNOS5250_REV_1_0) {
		for (i = 0; i < ARRAY_SIZE(exynos52xx_pmu_config_gps); i++) {
			__raw_writel(exynos52xx_pmu_config_gps[i].val[mode],
					exynos52xx_pmu_config_gps[i].reg);
		}

	}

	if ((mode != SYS_AFTR) && (exynos4_is_c2c_use())) {
		pr_info("%s power mode enter with C2C Enabling\n"
				, (mode == SYS_LPA) ? "LPA" : "SLEEP");

		for (i = 0; i < ARRAY_SIZE(exynos52xx_pmu_c2c_config); i++) {
			__raw_writel(exynos52xx_pmu_c2c_config[i].val[mode],
					exynos52xx_pmu_c2c_config[i].reg);
		}
	}
}
示例#5
0
void exynos4_cpu_suspend(void)
{
	unsigned int tmp;

	if ((!soc_is_exynos4210()) && (exynos4_is_c2c_use())) {
		/* Gating CLK_IEM_APC & Enable CLK_SSS */
		tmp = __raw_readl(EXYNOS4_CLKGATE_IP_DMC);
		tmp &= ~(0x1 << 17);
		tmp |= (0x1 << 4);
		__raw_writel(tmp, EXYNOS4_CLKGATE_IP_DMC);

		/* Set MAX divider for PWI */
		tmp = __raw_readl(EXYNOS4_CLKDIV_DMC1);
		tmp |= (0xF << 8);
		__raw_writel(tmp, EXYNOS4_CLKDIV_DMC1);

		/* Set clock source for PWI */
		tmp = __raw_readl(EXYNOS4_CLKSRC_DMC);
		tmp &= ~EXYNOS4_CLKSRC_DMC_MASK;
		tmp |= ((0x6 << 16)|(0x1 << 12));
		__raw_writel(tmp, EXYNOS4_CLKSRC_DMC);
	}

	outer_flush_all();

#ifdef CONFIG_ARM_TRUSTZONE
	exynos_smc(SMC_CMD_SLEEP, 0, 0, 0);
#else
	/* issue the standby signal into the pm unit. */
	cpu_do_idle();
#endif
}
static void exynos5_pm_prepare(void)
{
	unsigned int tmp;

	if (exynos5_sleep_gpio_table_set)
		exynos5_sleep_gpio_table_set();

	/* Disable USE_RETENTION of JPEG_MEM_OPTION */
	tmp = __raw_readl(EXYNOS5_JPEG_MEM_OPTION);
	tmp &= ~EXYNOS5_OPTION_USE_RETENTION;
	__raw_writel(tmp, EXYNOS5_JPEG_MEM_OPTION);

	/* Set value of power down register for sleep mode */
	exynos5_sys_powerdown_conf(SYS_SLEEP);
	__raw_writel(S5P_CHECK_SLEEP, REG_INFORM1);

	/* ensure at least INFORM0 has the resume address */
	__raw_writel(virt_to_phys(s3c_cpu_resume), REG_INFORM0);

	if (exynos4_is_c2c_use()) {
		tmp = __raw_readl(EXYNOS5_INTRAM_MEM_OPTION);
		tmp &= ~EXYNOS5_OPTION_USE_RETENTION;
		__raw_writel(tmp, EXYNOS5_INTRAM_MEM_OPTION);
	}
}
void exynos4_sys_powerdown_conf(enum sys_powerdown mode)
{
	unsigned int count = entry_cnt;
	unsigned int tmp;

	for (; count > 0; count--){
		if(S5P_XUSBXTI_SYS != exynos4_pmu_config[count - 1].reg){
			__raw_writel(exynos4_pmu_config[count - 1].val[mode],
					exynos4_pmu_config[count - 1].reg);
		}
		else if(S5P_XUSBXTI_SYS == exynos4_pmu_config[count - 1].reg){
			//printk("++++++++++++Terry++++++++++call_flag=%d , mode=%d \n", tc4_get_call_flg(),mode);
			if((tc4_get_call_flg() != 1)||(mode != SYS_SLEEP)){
				//printk("%s ------Terry1--------close xclk------tc4_get_call_flg=%d---\n",__func__,tc4_get_call_flg());
				__raw_writel(exynos4_pmu_config[count - 1].val[mode],
						exynos4_pmu_config[count - 1].reg);
			}
			else
			{
				//printk("%s ------Terry2--------close xclk------tc4_get_call_flg=%d---\n",__func__,tc4_get_call_flg());
				__raw_writel(0x1, exynos4_pmu_config[count - 1].reg);
			}
		} 
	}

	if ((!soc_is_exynos4210()) && (exynos4_is_c2c_use())) {
		for (count = 0 ; count < ARRAY_SIZE(exynos4x12_c2c_pmu_conf) ; count++)
			__raw_writel(exynos4x12_c2c_pmu_conf[count].val[mode],
					exynos4x12_c2c_pmu_conf[count].reg);

		if (soc_is_exynos4212())
			__raw_writel(exynos4212_c2c_pmu_conf[0].val[mode],
					exynos4212_c2c_pmu_conf[0].reg);

		for (count = 0 ; count < ARRAY_SIZE(exynos4_config_for_c2c) ; count++) {
			printk("exynos4_config_for_c2c \n");

			tmp = __raw_readl(exynos4_config_for_c2c[count].reg);
			tmp |= exynos4_config_for_c2c[count].val;
			__raw_writel(tmp, exynos4_config_for_c2c[count].reg);
		}
	}
}
void exynos4_cpu_suspend(void)
{
	unsigned int tmp;

	if (soc_is_exynos4210()) {
		/* eMMC power off delay (hidden register)
		 * 0x10020988 => 0: 300msec, 1: 6msec
		 */
		__raw_writel(1, S5P_PMUREG(0x0988));
	}

	if ((!soc_is_exynos4210()) && (exynos4_is_c2c_use())) {
		/* Gating CLK_IEM_APC & Enable CLK_SSS */
		tmp = __raw_readl(EXYNOS4_CLKGATE_IP_DMC);
		tmp &= ~(0x1 << 17);
		tmp |= (0x1 << 4);
		__raw_writel(tmp, EXYNOS4_CLKGATE_IP_DMC);

		/* Set MAX divider for PWI */
		tmp = __raw_readl(EXYNOS4_CLKDIV_DMC1);
		tmp |= (0xF << 8);
		__raw_writel(tmp, EXYNOS4_CLKDIV_DMC1);

		/* Set clock source for PWI */
		tmp = __raw_readl(EXYNOS4_CLKSRC_DMC);
		tmp &= ~EXYNOS4_CLKSRC_DMC_MASK;
		tmp |= ((0x6 << 16)|(0x1 << 12));
		__raw_writel(tmp, EXYNOS4_CLKSRC_DMC);
	}

	outer_flush_all();

	/* Disable the full line of zero */
	disable_cache_foz();
#ifdef CONFIG_ARM_TRUSTZONE
	exynos_smc(SMC_CMD_SLEEP, 0, 0, 0);
#else
	/* issue the standby signal into the pm unit. */
	cpu_do_idle();
#endif
}
示例#9
0
static void exynos4_pm_resume(void)
{
	unsigned long tmp;
	void __iomem *inform1;

	/* If PMU failed while entering sleep mode, WFI will be
	 * ignored by PMU and then exiting cpu_do_idle().
	 * S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically
	 * in this situation.
	 */
	tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
	if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) {
		tmp |= S5P_CENTRAL_LOWPWR_CFG;
		__raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
		/* No need to perform below restore code */
		pr_info("%s: early_wakeup\n", __func__);
		goto early_wakeup;
	}

	/* For release retention */

	__raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION);
	__raw_writel((1 << 28), S5P_PAD_RET_GPIO_OPTION);
	__raw_writel((1 << 28), S5P_PAD_RET_UART_OPTION);
	__raw_writel((1 << 28), S5P_PAD_RET_MMCA_OPTION);
	__raw_writel((1 << 28), S5P_PAD_RET_MMCB_OPTION);
	__raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION);
	__raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION);

	s3c_pm_do_restore(exynos4_regs_save, ARRAY_SIZE(exynos4_regs_save));
	if (soc_is_exynos4210())
		s3c_pm_do_restore(exynos4210_regs_save,
					ARRAY_SIZE(exynos4210_regs_save));
	else
		s3c_pm_do_restore(exynos4x12_regs_save,
					ARRAY_SIZE(exynos4x12_regs_save));

	if (!exynos4_is_c2c_use())
		s3c_pm_do_restore_core(exynos4_core_save, ARRAY_SIZE(exynos4_core_save));
	else {
		if (!soc_is_exynos4210()) {
			/* Gating CLK_SSS */
			tmp = __raw_readl(EXYNOS4_CLKGATE_IP_DMC);
			tmp &= ~(0x1 << 4);
			__raw_writel(tmp, EXYNOS4_CLKGATE_IP_DMC);
		}
	}

	tmp = __raw_readl(S5P_WAKEUP_STAT);
	if (WARN_ON(!tmp) && soc_is_exynos4412()) {
		__raw_writel(__raw_readl(S5P_EINT_PEND(0)), S5P_EINT_PEND(0));
		__raw_writel(__raw_readl(S5P_EINT_PEND(1)), S5P_EINT_PEND(1));
		__raw_writel(__raw_readl(S5P_EINT_PEND(2)), S5P_EINT_PEND(2));
		__raw_writel(__raw_readl(S5P_EINT_PEND(3)), S5P_EINT_PEND(3));
		__raw_writel(0x01010001, S5P_ARM_CORE_OPTION(0));
		__raw_writel(0x00000001, S5P_ARM_CORE_OPTION(1));
		__raw_writel(0x00000001, S5P_ARM_CORE_OPTION(2));
		__raw_writel(0x00000001, S5P_ARM_CORE_OPTION(3));
	}

#ifdef CONFIG_HAVE_ARM_SCU
	scu_enable(S5P_VA_SCU);
#endif

#ifdef CONFIG_CACHE_L2X0
	if (trustzone_on()) {
		/*
		 * Restore for Outer cache
		 */
		exynos_smc(SMC_CMD_L2X0SETUP1, exynos4_l2cc_save[0].val,
					       exynos4_l2cc_save[1].val,
					       exynos4_l2cc_save[2].val);

		exynos_smc(SMC_CMD_L2X0SETUP2,
				L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN,
				0x7C470001, 0xC200FFFF);

		exynos_smc(SMC_CMD_L2X0INVALL, 0, 0, 0);
		exynos_smc(SMC_CMD_L2X0CTRL, 1, 0, 0);
	} else {
		s3c_pm_do_restore_core(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save));
		outer_inv_all();
		/* enable L2X0*/
		writel_relaxed(1, S5P_VA_L2CC + L2X0_CTRL);
	}
#endif

early_wakeup:
	if (!soc_is_exynos4210())
		exynos4_reset_assert_ctrl(1);

#ifdef CONFIG_CACHE_L2X0
	/* Enable the full line of zero */
	enable_cache_foz();
#endif

	if (trustzone_on()) {
		inform1 = S5P_VA_SYSRAM_NS + 0xC;
	} else {
		inform1 = S5P_INFORM1;
	}

	/* Clear Check mode */
	__raw_writel(0x0, inform1);

	return;
}
static void exynos4_pm_resume(void)
{
	unsigned long tmp;

	/* If PMU failed while entering sleep mode, WFI will be
	 * ignored by PMU and then exiting cpu_do_idle().
	 * S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically
	 * in this situation.
	 */
	tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
	if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) {
		tmp |= S5P_CENTRAL_LOWPWR_CFG;
		__raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
		/* No need to perform below restore code */
		pr_info("%s: early_wakeup\n", __func__);
		goto early_wakeup;
	}

	/* For release retention */

	__raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION);
	__raw_writel((1 << 28), S5P_PAD_RET_GPIO_OPTION);
	__raw_writel((1 << 28), S5P_PAD_RET_UART_OPTION);
	__raw_writel((1 << 28), S5P_PAD_RET_MMCA_OPTION);
	__raw_writel((1 << 28), S5P_PAD_RET_MMCB_OPTION);
	__raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION);
	__raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION);

	s3c_pm_do_restore(exynos4_regs_save, ARRAY_SIZE(exynos4_regs_save));
	if (soc_is_exynos4210())
		s3c_pm_do_restore(exynos4210_regs_save,
					ARRAY_SIZE(exynos4210_regs_save));
	else
		s3c_pm_do_restore(exynos4x12_regs_save,
					ARRAY_SIZE(exynos4x12_regs_save));

#if defined(CONFIG_MACH_M0_CTC)
{
	if (max7693_muic_cp_usb_state()) {
		if (system_rev < 11) {
			gpio_direction_output(GPIO_USB_BOOT_EN, 1);
		} else if (system_rev == 11) {
			gpio_direction_output(GPIO_USB_BOOT_EN, 1);
			gpio_direction_output(GPIO_USB_BOOT_EN_REV06, 1);
		} else {
			gpio_direction_output(GPIO_USB_BOOT_EN_REV06, 1);
		}
	}
}
#endif

	CHECK_POINT;

	if (!exynos4_is_c2c_use())
		s3c_pm_do_restore_core(exynos4_core_save, ARRAY_SIZE(exynos4_core_save));
	else {
		if (!soc_is_exynos4210()) {
			/* Gating CLK_SSS */
			tmp = __raw_readl(EXYNOS4_CLKGATE_IP_DMC);
			tmp &= ~(0x1 << 4);
			__raw_writel(tmp, EXYNOS4_CLKGATE_IP_DMC);
		}
	}

	/* For the suspend-again to check the value */
	s3c_suspend_wakeup_stat = __raw_readl(S5P_WAKEUP_STAT);

	CHECK_POINT;

	scu_enable(S5P_VA_SCU);

	CHECK_POINT;

#ifdef CONFIG_CACHE_L2X0
#ifdef CONFIG_ARM_TRUSTZONE
	/*
	 * Restore for Outer cache
	 */
	exynos_smc(SMC_CMD_L2X0SETUP1, exynos4_l2cc_save[0].val,
				       exynos4_l2cc_save[1].val,
				       exynos4_l2cc_save[2].val);

	CHECK_POINT;

	exynos_smc(SMC_CMD_L2X0SETUP2,
			L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN,
			0x7C470001, 0xC200FFFF);

	CHECK_POINT;

	exynos_smc(SMC_CMD_L2X0INVALL, 0, 0, 0);

	CHECK_POINT;

	exynos_smc(SMC_CMD_L2X0CTRL, 1, 0, 0);
#else
	s3c_pm_do_restore_core(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save));
	outer_inv_all();
	/* enable L2X0*/
	writel_relaxed(1, S5P_VA_L2CC + L2X0_CTRL);
#endif
	/* Enable the full line of zero */
	enable_cache_foz();
#endif

	CHECK_POINT;

early_wakeup:
	if (!soc_is_exynos4210())
		exynos4_reset_assert_ctrl(1);

	CHECK_POINT;

	/* Clear Check mode */
	__raw_writel(0x0, REG_INFORM1);

	return;
}
示例#11
0
static void exynos4_pm_resume(void)
{
	unsigned long tmp;

	/* If PMU failed while entering sleep mode, WFI will be
	 * ignored by PMU and then exiting cpu_do_idle().
	 * S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically
	 * in this situation.
	 */
	tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
	if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) {
		tmp |= S5P_CENTRAL_LOWPWR_CFG;
		__raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
		/* No need to perform below restore code */
		goto early_wakeup;
	}

	/* For release retention */

	__raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION);
	__raw_writel((1 << 28), S5P_PAD_RET_GPIO_OPTION);
	__raw_writel((1 << 28), S5P_PAD_RET_UART_OPTION);
	__raw_writel((1 << 28), S5P_PAD_RET_MMCA_OPTION);
	__raw_writel((1 << 28), S5P_PAD_RET_MMCB_OPTION);
	__raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION);
	__raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION);

	if (!exynos4_is_c2c_use())
		s3c_pm_do_restore_core(exynos4_core_save, ARRAY_SIZE(exynos4_core_save));
	else {
		if (!soc_is_exynos4210()) {
			/* Gating CLK_SSS */
			tmp = __raw_readl(EXYNOS4_CLKGATE_IP_DMC);
			tmp &= ~(0x1 << 4);
			__raw_writel(tmp, EXYNOS4_CLKGATE_IP_DMC);
		}
	}

	exynos4_scu_enable(S5P_VA_SCU);

#ifdef CONFIG_CACHE_L2X0
#ifdef CONFIG_ARM_TRUSTZONE
	/*
	 * Restore for Outer cache
	 */
	exynos_smc(SMC_CMD_L2X0SETUP1, exynos4_l2cc_save[0].val,
				       exynos4_l2cc_save[1].val,
				       exynos4_l2cc_save[2].val);

	exynos_smc(SMC_CMD_L2X0SETUP2,
			L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN,
			0x7C470001, 0xC200FFFF);

	exynos_smc(SMC_CMD_L2X0INVALL, 0, 0, 0);
	exynos_smc(SMC_CMD_L2X0CTRL, 1, 0, 0);
#else
	s3c_pm_do_restore_core(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save));
	outer_inv_all();
	/* enable L2X0*/
	writel_relaxed(1, S5P_VA_L2CC + L2X0_CTRL);
#endif
#endif

early_wakeup:
	if (!soc_is_exynos4210())
		exynos4_reset_assert_ctrl(1);

#ifdef CONFIG_CACHE_L2X0
	/* Enable the full line of zero */
	enable_cache_foz();
#endif

	/* Clear Check mode */
	__raw_writel(0x0, REG_INFORM1);

	return;
}