static int exynos4_usb_phy20_init(struct platform_device *pdev)
{
u32 phypwr, phyclk, rstcon;
if (!strcmp(pdev->name, "s5p-ehci"))
set_bit(HOST_PHY_EHCI, &usb_phy_control.usage);
else if (!strcmp(pdev->name, "s5p-ohci"))
set_bit(HOST_PHY_OHCI, &usb_phy_control.usage);
else if (!strcmp(pdev->name, "s3c-usbgadget"))
set_bit(HOST_PHY_DEVICE, &usb_phy_control.usage);
dev_info(&pdev->dev, "usb phy usage(%ld)\n", usb_phy_control.usage);
if (exynos4_usb_phy20_is_on()) {
dev_err(&pdev->dev, "Already power on PHY\n");
return 0;
}
/*
* set XuhostOVERCUR to in-active by controlling ET6PUD[15:14]
* 0x0 : pull-up/down disabled
* 0x1 : pull-down enabled
* 0x2 : reserved
* 0x3 : pull-up enabled
*/
writel((__raw_readl(ETC6PUD) & ~(0x3 << 14)) | (0x3 << 14),
ETC6PUD);
exynos_usb_phy_control(USB_PHY
| USB_PHY_HSIC0
| USB_PHY_HSIC1,
PHY_ENABLE);
/* USB MUX change from Device to Host */
exynos_usb_mux_change(pdev, 1);
/* set clock frequency for PLL */
phyclk = exynos_usb_phy_set_clock(pdev);
/* COMMON Block configuration during suspend */
phyclk &= ~(PHY0_COMMON_ON_N);
#ifdef CONFIG_USB_OHCI_S5P
phyclk |= PHY1_COMMON_ON_N;
#else
phyclk &= ~(PHY1_COMMON_ON_N);
#endif
writel(phyclk, EXYNOS4_PHYCLK);
/* set to normal of Device */
phypwr = readl(EXYNOS4_PHYPWR) & ~PHY0_NORMAL_MASK;
writel(phypwr, EXYNOS4_PHYPWR);
/* set to normal of Host */
phypwr = readl(EXYNOS4_PHYPWR);
phypwr &= ~(PHY1_STD_NORMAL_MASK
| EXYNOS4212_HSIC0_NORMAL_MASK
| EXYNOS4212_HSIC1_NORMAL_MASK);
writel(phypwr, EXYNOS4_PHYPWR);
/* reset both PHY and Link of Device */
rstcon = readl(EXYNOS4_RSTCON) | PHY0_SWRST_MASK;
writel(rstcon, EXYNOS4_RSTCON);
udelay(10);
rstcon &= ~PHY0_SWRST_MASK;
writel(rstcon, EXYNOS4_RSTCON);
/* reset both PHY and Link of Host */
rstcon = readl(EXYNOS4_RSTCON)
| EXYNOS4212_HOST_LINK_PORT_SWRST_MASK
| EXYNOS4212_PHY1_SWRST_MASK;
writel(rstcon, EXYNOS4_RSTCON);
udelay(10);
rstcon &= ~(EXYNOS4212_HOST_LINK_PORT_SWRST_MASK
| EXYNOS4212_PHY1_SWRST_MASK);
writel(rstcon, EXYNOS4_RSTCON);
udelay(80);
return 0;
}
static int exynos4_usb_phy20_init(struct platform_device *pdev)
{
u32 phypwr, phyclk, rstcon;
//printk("[exynos4_usb_phy20_init]++++++++++++++\n");
atomic_inc(&host_usage);
if (exynos4_usb_phy20_is_on()) {
//dev_err(&pdev->dev, "Already power on PHY\n");
/*diog.zhao,0614,remove*/
//if(USB_PHY_L2 == usb_phy_control.status)
//return -1;
return 0;
}
if(USB_PHY_L0 == usb_phy_control.status)
return 0;
/*
* set XuhostOVERCUR to in-active by controlling ET6PUD[15:14]
* 0x0 : pull-up/down disabled
* 0x1 : pull-down enabled
* 0x2 : reserved
* 0x3 : pull-up enabled
*/
writel((__raw_readl(ETC6PUD) & ~(0x3 << 14)) | (0x3 << 14),
ETC6PUD);
exynos_usb_phy_control(USB_PHY
| USB_PHY_HSIC0
| USB_PHY_HSIC1,
PHY_ENABLE);
/* USB MUX change from Device to Host */
exynos_usb_mux_change(pdev, 1);
/* set clock frequency for PLL */
phyclk = exynos_usb_phy_set_clock(pdev);
/* COMMON Block configuration during suspend */
phyclk &= ~(PHY0_COMMON_ON_N | PHY1_COMMON_ON_N);
writel(phyclk, EXYNOS4_PHYCLK);
/* set to normal of Device */
phypwr = readl(EXYNOS4_PHYPWR) & ~PHY0_NORMAL_MASK;
writel(phypwr, EXYNOS4_PHYPWR);
/* set to normal of Host */
phypwr = readl(EXYNOS4_PHYPWR);
phypwr &= ~(PHY1_STD_NORMAL_MASK
| EXYNOS4212_HSIC0_NORMAL_MASK
| EXYNOS4212_HSIC1_NORMAL_MASK);
writel(phypwr, EXYNOS4_PHYPWR);
/* reset both PHY and Link of Device */
rstcon = readl(EXYNOS4_RSTCON) | PHY0_SWRST_MASK;
writel(rstcon, EXYNOS4_RSTCON);
udelay(10);
rstcon &= ~PHY0_SWRST_MASK;
writel(rstcon, EXYNOS4_RSTCON);
/* reset both PHY and Link of Host */
rstcon = readl(EXYNOS4_RSTCON)
| EXYNOS4212_HOST_LINK_PORT_SWRST_MASK
| EXYNOS4212_PHY1_SWRST_MASK;
writel(rstcon, EXYNOS4_RSTCON);
udelay(10);
rstcon &= ~(EXYNOS4212_HOST_LINK_PORT_SWRST_MASK
| EXYNOS4212_PHY1_SWRST_MASK);
writel(rstcon, EXYNOS4_RSTCON);
udelay(80);
usb_phy_control.status = USB_PHY_L0;
return 0;
}
