void nmi_watchdog_tick(struct cpu_user_regs * regs)
{
unsigned int sum = this_cpu(nmi_timer_ticks);
if ( (this_cpu(last_irq_sums) == sum) &&
!atomic_read(&watchdog_disable_count) )
{
/*
* Ayiee, looks like this CPU is stuck ... wait a few IRQs (5 seconds)
* before doing the oops ...
*/
this_cpu(alert_counter)++;
if ( this_cpu(alert_counter) == 5*nmi_hz )
{
console_force_unlock();
printk("Watchdog timer detects that CPU%d is stuck!\n",
smp_processor_id());
fatal_trap(TRAP_nmi, regs);
}
}
else
{
this_cpu(last_irq_sums) = sum;
this_cpu(alert_counter) = 0;
}
if ( nmi_perfctr_msr )
{
if ( nmi_perfctr_msr == MSR_P4_IQ_PERFCTR0 )
{
/*
* P4 quirks:
* - An overflown perfctr will assert its interrupt
* until the OVF flag in its CCCR is cleared.
* - LVTPC is masked on interrupt and must be
* unmasked by the LVTPC handler.
*/
wrmsrl(MSR_P4_IQ_CCCR0, nmi_p4_cccr_val);
apic_write(APIC_LVTPC, APIC_DM_NMI);
}
else if ( nmi_perfctr_msr == MSR_P6_PERFCTR0 )
{
/*
* Only P6 based Pentium M need to re-unmask the apic vector but
* it doesn't hurt other P6 variants.
*/
apic_write(APIC_LVTPC, APIC_DM_NMI);
}
write_watchdog_counter(NULL);
}
}
