int ft_board_setup(void *blob, bd_t *bd) { u64 base[CONFIG_NR_DRAM_BANKS]; u64 size[CONFIG_NR_DRAM_BANKS]; u8 reg; /* fixup DT for the two DDR banks */ base[0] = gd->bd->bi_dram[0].start; size[0] = gd->bd->bi_dram[0].size; base[1] = gd->bd->bi_dram[1].start; size[1] = gd->bd->bi_dram[1].size; fdt_fixup_memory_banks(blob, base, size, 2); ft_cpu_setup(blob, bd); #ifdef CONFIG_SYS_DPAA_FMAN fdt_fixup_fman_ethernet(blob); fdt_fixup_board_enet(blob); #endif reg = QIXIS_READ(brdcfg[0]); reg = (reg & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; /* Disable IFC if QSPI is enabled */ if (reg == 0xF) do_fixup_by_compat(blob, "fsl,ifc", "status", "disabled", 8 + 1, 1); return 0; }
int ft_board_setup(void *blob, bd_t *bd) { phys_addr_t base; phys_size_t size; ft_cpu_setup(blob, bd); base = getenv_bootm_low(); size = getenv_bootm_size(); fdt_fixup_memory(blob, (u64)base, (u64)size); #ifdef CONFIG_PCI pci_of_setup(blob, bd); #endif fdt_fixup_liodn(blob); fdt_fixup_dr_usb(blob, bd); #ifdef CONFIG_SYS_DPAA_FMAN fdt_fixup_fman_ethernet(blob); fdt_fixup_board_enet(blob); #endif return 0; }
int ft_board_setup(void *blob, bd_t *bd) { phys_addr_t base; phys_size_t size; ft_cpu_setup(blob, bd); base = env_get_bootm_low(); size = env_get_bootm_size(); fdt_fixup_memory(blob, (u64)base, (u64)size); #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) fsl_fdt_fixup_dr_usb(blob, bd); #endif #ifdef CONFIG_PCI pci_of_setup(blob, bd); #endif fdt_fixup_liodn(blob); #ifdef CONFIG_SYS_DPAA_FMAN fdt_fixup_fman_ethernet(blob); fdt_fixup_fman_mac_addresses(blob); #endif return 0; }
int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); #ifdef CONFIG_SYS_DPAA_FMAN fdt_fixup_fman_ethernet(blob); #endif return 0; }
void ft_board_setup(void *blob, bd_t *bd) { phys_addr_t base; phys_size_t size; ft_cpu_setup(blob, bd); base = getenv_bootm_low(); size = getenv_bootm_size(); fdt_fixup_memory(blob, (u64)base, (u64)size); fdt_fixup_fman_ethernet(blob); }
int ft_board_setup(void *blob, bd_t *bd) { u64 base[CONFIG_NR_DRAM_BANKS]; u64 size[CONFIG_NR_DRAM_BANKS]; /* fixup DT for the two DDR banks */ base[0] = gd->bd->bi_dram[0].start; size[0] = gd->bd->bi_dram[0].size; base[1] = gd->bd->bi_dram[1].start; size[1] = gd->bd->bi_dram[1].size; fdt_fixup_memory_banks(blob, base, size, 2); ft_cpu_setup(blob, bd); #ifdef CONFIG_SYS_DPAA_FMAN fdt_fixup_fman_ethernet(blob); #endif return 0; }
int ft_board_setup(void *blob, bd_t *bd) { phys_addr_t base; phys_size_t size; ft_cpu_setup(blob, bd); base = getenv_bootm_low(); size = getenv_bootm_size(); fdt_fixup_memory(blob, (u64)base, (u64)size); #ifdef CONFIG_HAS_FSL_DR_USB fdt_fixup_dr_usb(blob, bd); #endif fdt_fixup_fman_ethernet(blob); return 0; }
void ft_board_setup(void *blob, bd_t *bd) { phys_addr_t base; phys_size_t size; ft_cpu_setup(blob, bd); base = getenv_bootm_low(); size = getenv_bootm_size(); fdt_fixup_memory(blob, (u64)base, (u64)size); /* By default NOR is on, and NAND is disabled */ #ifdef CONFIG_NAND_U_BOOT do_fixup_by_path_string(blob, "nor_flash", "status", "disabled"); do_fixup_by_path_string(blob, "nand_flash", "status", "okay"); #endif #ifdef CONFIG_HAS_FSL_DR_USB fdt_fixup_dr_usb(blob, bd); #endif fdt_fixup_fman_ethernet(blob); }