static int
fdt_aintc_decode_ic(phandle_t node, pcell_t *intr, int *interrupt, int *trig,
int *pol)
{
if (!fdt_is_compatible(node, "ti,aintc") &&
!fdt_is_compatible(node, "ti,am33xx-intc"))
return (ENXIO);
*interrupt = fdt32_to_cpu(intr[0]);
*trig = INTR_TRIGGER_CONFORM;
*pol = INTR_POLARITY_CONFORM;
return (0);
}
int
fdt_immr_addr(vm_offset_t immr_va)
{
phandle_t node;
u_long base, size;
int r;
/*
* Try to access the SOC node directly i.e. through /aliases/.
*/
if ((node = OF_finddevice("soc")) != 0)
if (fdt_is_compatible(node, "simple-bus"))
goto moveon;
/*
* Find the node the long way.
*/
if ((node = OF_finddevice("/")) == 0)
return (ENXIO);
if ((node = fdt_find_compatible(node, "simple-bus", 0)) == 0)
return (ENXIO);
moveon:
if ((r = fdt_get_range(node, 0, &base, &size)) == 0) {
fdt_immr_pa = base;
fdt_immr_va = immr_va;
fdt_immr_size = size;
}
return (r);
}
static int
fdt_aintc_decode_ic(phandle_t node, pcell_t *intr, int *interrupt, int *trig,
int *pol)
{
int offset;
if (fdt_is_compatible(node, "allwinner,sun4i-ic"))
offset = 0;
else if (fdt_is_compatible(node, "arm,gic"))
offset = 32;
else
return (ENXIO);
*interrupt = fdt32_to_cpu(intr[0]) + offset;
*trig = INTR_TRIGGER_CONFORM;
*pol = INTR_POLARITY_CONFORM;
return (0);
}
static int
rk30_gpio_init(void)
{
phandle_t child, parent, root, ctrl;
pcell_t gpios[MAX_PINS_PER_NODE * GPIOS_PROP_CELLS];
struct gpio_ctrl_entry *e;
int len, rv;
root = OF_finddevice("/");
len = 0;
parent = root;
/* Traverse through entire tree to find nodes with 'gpios' prop */
for (child = OF_child(parent); child != 0; child = OF_peer(child)) {
/* Find a 'leaf'. Start the search from this node. */
while (OF_child(child)) {
parent = child;
child = OF_child(child);
}
if ((len = OF_getproplen(child, "gpios")) > 0) {
if (len > sizeof(gpios))
return (ENXIO);
/* Get 'gpios' property. */
OF_getprop(child, "gpios", &gpios, len);
e = (struct gpio_ctrl_entry *)&gpio_controllers;
/* Find and call a handler. */
for (; e->compat; e++) {
/*
* First cell of 'gpios' property should
* contain a ref. to a node defining GPIO
* controller.
*/
ctrl = OF_node_from_xref(fdt32_to_cpu(gpios[0]));
if (fdt_is_compatible(ctrl, e->compat))
/* Call a handler. */
if ((rv = e->handler(ctrl,
(pcell_t *)&gpios, len)))
return (rv);
}
}
if (OF_peer(child) == 0) {
/* No more siblings. */
child = parent;
parent = OF_parent(child);
}
}
return (0);
}
static const struct ofw_compat_data *
uart_fdt_find_compatible(phandle_t node, const struct ofw_compat_data *cd)
{
const struct ofw_compat_data *ocd;
for (ocd = cd; ocd->ocd_str != NULL; ocd++) {
if (fdt_is_compatible(node, ocd->ocd_str))
return (ocd);
}
return (NULL);
}
static const struct ofw_compat_data *
aw_ccu_search_compatible(void)
{
const struct ofw_compat_data *compat;
phandle_t root;
root = OF_finddevice("/");
for (compat = compat_data; compat->ocd_str != NULL; compat++)
if (fdt_is_compatible(root, compat->ocd_str))
break;
return (compat);
}
static int
fdt_intc_decode_ic(phandle_t node, pcell_t *intr, int *interrupt, int *trig,
int *pol)
{
if (!fdt_is_compatible(node, "broadcom,bcm2835-armctrl-ic"))
return (ENXIO);
*interrupt = fdt32_to_cpu(intr[0]);
*trig = INTR_TRIGGER_CONFORM;
*pol = INTR_POLARITY_CONFORM;
return (0);
}
static int
fdt_aic_decode_ic(phandle_t node, pcell_t *intr, int *interrupt, int *trig,
int *pol)
{
int offset;
if (fdt_is_compatible(node, "atmel,at91rm9200-aic"))
offset = 0;
else
return (ENXIO);
*interrupt = fdt32_to_cpu(intr[0]) + offset;
*trig = INTR_TRIGGER_CONFORM;
*pol = INTR_POLARITY_CONFORM;
return (0);
}
phandle_t
fdt_find_compatible(phandle_t start, const char *compat, int strict)
{
phandle_t child;
/*
* Traverse all children of 'start' node, and find first with
* matching 'compatible' property.
*/
for (child = OF_child(start); child != 0; child = OF_peer(child))
if (fdt_is_compatible(child, compat)) {
if (strict)
if (!fdt_is_compatible_strict(child, compat))
continue;
return (child);
}
return (0);
}
static int
fdt_pic_decode_openpic(phandle_t node, pcell_t *intr, int *interrupt,
int *trig, int *pol)
{
if (!fdt_is_compatible(node, "chrp,open-pic"))
return (ENXIO);
/*
* XXX The interrupt number read out from the MPC85XX device tree is
* already offset by 16 to reflect the 'internal' IRQ range shift on
* the OpenPIC.
*/
*interrupt = intr[0];
switch (intr[1]) {
case 0:
/* L to H edge */
*trig = INTR_TRIGGER_EDGE;
*pol = INTR_POLARITY_HIGH;
break;
case 1:
/* Active L level */
*trig = INTR_TRIGGER_LEVEL;
*pol = INTR_POLARITY_LOW;
break;
case 2:
/* Active H level */
*trig = INTR_TRIGGER_LEVEL;
*pol = INTR_POLARITY_HIGH;
break;
case 3:
/* H to L edge */
*trig = INTR_TRIGGER_EDGE;
*pol = INTR_POLARITY_LOW;
break;
default:
*trig = INTR_TRIGGER_CONFORM;
*pol = INTR_POLARITY_CONFORM;
}
return (0);
}
phandle_t
fdt_depth_search_compatible(phandle_t start, const char *compat, int strict)
{
phandle_t child, node;
/*
* Depth-search all descendants of 'start' node, and find first with
* matching 'compatible' property.
*/
for (node = OF_child(start); node != 0; node = OF_peer(node)) {
if (fdt_is_compatible(node, compat) &&
(strict == 0 || fdt_is_compatible_strict(node, compat))) {
return (node);
}
child = fdt_depth_search_compatible(node, compat, strict);
if (child != 0)
return (child);
}
return (0);
}
static int
fdt_pic_decode_iic(phandle_t node, pcell_t *intr, int *interrupt, int *trig,
int *pol)
{
if (!fdt_is_compatible(node, "chrp,iic"))
return (ENXIO);
*interrupt = intr[0];
switch (intr[1]) {
case 0:
/* Active L level */
*trig = INTR_TRIGGER_LEVEL;
*pol = INTR_POLARITY_LOW;
break;
case 1:
/* Active H level */
*trig = INTR_TRIGGER_LEVEL;
*pol = INTR_POLARITY_HIGH;
break;
case 2:
/* H to L edge */
*trig = INTR_TRIGGER_EDGE;
*pol = INTR_POLARITY_LOW;
break;
case 3:
/* L to H edge */
*trig = INTR_TRIGGER_EDGE;
*pol = INTR_POLARITY_HIGH;
break;
default:
*trig = INTR_TRIGGER_CONFORM;
*pol = INTR_POLARITY_CONFORM;
}
return (0);
}
static boolean_t
alpine_validate_cpu(u_int id, phandle_t child, u_int addr_cell, pcell_t *reg)
{
return fdt_is_compatible(child, "arm,cortex-a15");
}
static int
qman_portals_fdt_attach(device_t dev)
{
struct dpaa_portals_softc *sc;
struct resource_list_entry *rle;
phandle_t node, child, cpu_node;
vm_paddr_t portal_pa;
vm_size_t portal_size;
uint32_t addr, size;
ihandle_t cpu;
int cpu_num, cpus, intr_rid;
struct dpaa_portals_devinfo di;
struct ofw_bus_devinfo ofw_di = {};
cpus = 0;
sc = device_get_softc(dev);
sc->sc_dev = dev;
node = ofw_bus_get_node(dev);
get_addr_props(node, &addr, &size);
/* Find portals tied to CPUs */
for (child = OF_child(node); child != 0; child = OF_peer(child)) {
if (!fdt_is_compatible(child, "fsl,qman-portal")) {
continue;
}
/* Checkout related cpu */
if (OF_getprop(child, "cpu-handle", (void *)&cpu,
sizeof(cpu)) <= 0) {
continue;
}
/* Acquire cpu number */
cpu_node = OF_instance_to_package(cpu);
if (OF_getencprop(cpu_node, "reg", &cpu_num, sizeof(cpu_num)) <= 0) {
device_printf(dev, "Could not retrieve CPU number.\n");
return (ENXIO);
}
cpus++;
if (cpus > MAXCPU)
break;
if (ofw_bus_gen_setup_devinfo(&ofw_di, child) != 0) {
device_printf(dev, "could not set up devinfo\n");
continue;
}
resource_list_init(&di.di_res);
if (ofw_bus_reg_to_rl(dev, child, addr, size, &di.di_res)) {
device_printf(dev, "%s: could not process 'reg' "
"property\n", ofw_di.obd_name);
ofw_bus_gen_destroy_devinfo(&ofw_di);
continue;
}
if (ofw_bus_intr_to_rl(dev, child, &di.di_res, &intr_rid)) {
device_printf(dev, "%s: could not process "
"'interrupts' property\n", ofw_di.obd_name);
resource_list_free(&di.di_res);
ofw_bus_gen_destroy_devinfo(&ofw_di);
continue;
}
di.di_intr_rid = intr_rid;
ofw_reg_to_paddr(child, 0, &portal_pa, &portal_size, NULL);
rle = resource_list_find(&di.di_res, SYS_RES_MEMORY, 0);
if (sc->sc_dp_pa == 0)
sc->sc_dp_pa = portal_pa - rle->start;
portal_size = rle->end + 1;
rle = resource_list_find(&di.di_res, SYS_RES_MEMORY, 1);
portal_size = ulmax(rle->end + 1, portal_size);
sc->sc_dp_size = ulmax(sc->sc_dp_size, portal_size);
if (dpaa_portal_alloc_res(dev, &di, cpu_num))
goto err;
}
ofw_bus_gen_destroy_devinfo(&ofw_di);
return (qman_portals_attach(dev));
err:
resource_list_free(&di.di_res);
ofw_bus_gen_destroy_devinfo(&ofw_di);
qman_portals_detach(dev);
return (ENXIO);
}
int
uart_cpu_getdev(int devtype, struct uart_devinfo *di)
{
char buf[64];
struct uart_class *class;
phandle_t node, chosen;
pcell_t shift, br, rclk;
u_long start, size;
int err;
uart_bus_space_mem = fdtbus_bs_tag;
uart_bus_space_io = NULL;
/* Allow overriding the FDT uning the environment. */
class = &uart_ns8250_class;
err = uart_getenv(devtype, di, class);
if (!err)
return (0);
if (devtype != UART_DEV_CONSOLE)
return (ENXIO);
/*
* Retrieve /chosen/std{in,out}.
*/
if ((chosen = OF_finddevice("/chosen")) == 0)
return (ENXIO);
if (OF_getprop(chosen, "stdin", buf, sizeof(buf)) <= 0)
return (ENXIO);
if ((node = OF_finddevice(buf)) == 0)
return (ENXIO);
if (OF_getprop(chosen, "stdout", buf, sizeof(buf)) <= 0)
return (ENXIO);
if (OF_finddevice(buf) != node)
/* Only stdin == stdout is supported. */
return (ENXIO);
/*
* Retrieve serial attributes.
*/
uart_fdt_get_shift(node, &shift);
if (OF_getprop(node, "current-speed", &br, sizeof(br)) <= 0)
br = 0;
br = fdt32_to_cpu(br);
if ((err = uart_fdt_get_clock(node, &rclk)) != 0)
return (err);
/*
* Finalize configuration.
*/
class = &uart_quicc_class;
if (fdt_is_compatible(node, "ns16550"))
class = &uart_ns8250_class;
di->bas.chan = 0;
di->bas.regshft = (u_int)shift;
di->baudrate = 0;
di->bas.rclk = (u_int)rclk;
di->ops = uart_getops(class);
di->databits = 8;
di->stopbits = 1;
di->parity = UART_PARITY_NONE;
di->bas.bst = uart_bus_space_mem;
err = fdt_regsize(node, &start, &size);
if (err)
return (ENXIO);
start += fdt_immr_va;
return (bus_space_map(di->bas.bst, start, size, 0, &di->bas.bsh));
}
