static int pic32_sdhci_probe(struct udevice *dev)
{
struct sdhci_host *host = dev_get_priv(dev);
const void *fdt = gd->fdt_blob;
u32 f_min_max[2];
fdt_addr_t addr;
fdt_size_t size;
int ret;
addr = fdtdec_get_addr_size(fdt, dev->of_offset, "reg", &size);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
host->ioaddr = ioremap(addr, size);
host->name = dev->name;
host->quirks = SDHCI_QUIRK_NO_HISPD_BIT | SDHCI_QUIRK_NO_CD;
host->bus_width = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
"bus-width", 4);
ret = fdtdec_get_int_array(gd->fdt_blob, dev->of_offset,
"clock-freq-min-max", f_min_max, 2);
if (ret) {
printf("sdhci: clock-freq-min-max not found\n");
return ret;
}
ret = add_sdhci(host, f_min_max[1], f_min_max[0]);
if (ret)
return ret;
host->mmc->dev = dev;
return 0;
}
int dram_init(void)
{
#ifdef CONFIG_OF_CONTROL
int node;
fdt_addr_t addr;
fdt_size_t size;
const void *blob = gd->fdt_blob;
node = fdt_node_offset_by_prop_value(blob, -1, "device_type",
"memory", 7);
if (node == -FDT_ERR_NOTFOUND) {
debug("ZYNQ DRAM: Can't get memory node\n");
return -1;
}
addr = fdtdec_get_addr_size(blob, node, "reg", &size);
if (addr == FDT_ADDR_T_NONE || size == 0) {
debug("ZYNQ DRAM: Can't get base address or size\n");
return -1;
}
gd->ram_size = size;
#else
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
#endif
zynq_ddrc_init();
return 0;
}
static int do_pinctr_pin(const void *blob, int child, const char *node_name)
{
int len;
fdt_addr_t base_addr;
fdt_size_t size;
const u32 *cell;
u32 offset, value;
base_addr = fdtdec_get_addr_size(blob, child, "reg", &size);
if (base_addr != FDT_ADDR_T_NONE) {
cell = fdt_getprop(blob, child, "pinctrl-single,pins", &len);
if (!cell || len <= 0)
return -EFAULT;
debug("%p %d\n", cell, len);
for (; len > 0; len -= (2 * sizeof(u32))) {
offset = fdt32_to_cpu(*cell++);
value = fdt32_to_cpu(*cell++);
debug("<0x%x 0x%x>\n", offset, value);
writel(value, base_addr + offset);
}
return 0;
}
return -EFAULT;
}
int spi_flash_decode_fdt(const void *blob, struct spi_flash *flash)
{
fdt_addr_t addr;
fdt_size_t size;
int node;
struct spansion_spi_flash *spsn;
/* If there is no node, do nothing */
node = fdtdec_next_compatible(blob, 0, COMPAT_GENERIC_SPI_FLASH);
if (node < 0)
return 0;
addr = fdtdec_get_addr_size(blob, node, "memory-map", &size);
if (addr == FDT_ADDR_T_NONE) {
debug("%s: Cannot decode address\n", __func__);
return 0;
}
if (spsn->size != size) {
debug("%s: Memory map must cover entire device\n", __func__);
return -1;
}
spsn->memory_map = (void *)addr;
return 0;
}
static int pic32_uart_probe(struct udevice *dev)
{
struct pic32_uart_priv *priv = dev_get_priv(dev);
struct clk clk;
fdt_addr_t addr;
fdt_size_t size;
int ret;
/* get address */
addr = fdtdec_get_addr_size(gd->fdt_blob, dev->of_offset, "reg", &size);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
priv->base = ioremap(addr, size);
/* get clock rate */
ret = clk_get_by_index(dev, 0, &clk);
if (ret < 0)
return ret;
priv->uartclk = clk_get_rate(&clk);
clk_free(&clk);
/* initialize serial */
return pic32_serial_init(priv->base, priv->uartclk, CONFIG_BAUDRATE);
}
static int uniphier_gpio_probe(struct udevice *dev)
{
struct uniphier_gpio_priv *priv = dev_get_priv(dev);
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
DECLARE_GLOBAL_DATA_PTR;
fdt_addr_t addr;
fdt_size_t size;
unsigned int tmp;
addr = fdtdec_get_addr_size(gd->fdt_blob, dev->of_offset, "reg",
&size);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
priv->base = map_sysmem(addr, size);
if (!priv->base)
return -ENOMEM;
uc_priv->gpio_count = UNIPHIER_GPIO_PORTS_PER_BANK;
tmp = (addr & 0xfff);
/* Unfortunately, there is a register hole at offset 0x90-0x9f. */
if (tmp > 0x90)
tmp -= 0x10;
snprintf(priv->bank_name, sizeof(priv->bank_name) - 1,
"port%d-", (tmp - 8) / 8);
uc_priv->bank_name = priv->bank_name;
return 0;
}
int dram_init(void)
{
int node;
fdt_addr_t addr;
fdt_size_t size;
const void *blob = gd->fdt_blob;
node = fdt_node_offset_by_prop_value(blob, -1, "device_type",
"memory", 7);
if (node == -FDT_ERR_NOTFOUND) {
debug("DRAM: Can't get memory node\n");
return 1;
}
addr = fdtdec_get_addr_size(blob, node, "reg", &size);
if (addr == FDT_ADDR_T_NONE || size == 0) {
debug("DRAM: Can't get base address or size\n");
return 1;
}
ram_base = addr;
gd->ram_top = addr; /* In setup_dest_addr() is done +ram_size */
gd->ram_size = size;
return 0;
};
static int pic32_spi_probe(struct udevice *bus)
{
struct pic32_spi_priv *priv = dev_get_priv(bus);
struct dm_spi_bus *dm_spi = dev_get_uclass_priv(bus);
struct udevice *clkdev;
fdt_addr_t addr;
fdt_size_t size;
int ret;
debug("%s: %d, bus: %i\n", __func__, __LINE__, bus->seq);
addr = fdtdec_get_addr_size(gd->fdt_blob, bus->of_offset, "reg", &size);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
priv->regs = ioremap(addr, size);
if (!priv->regs)
return -EINVAL;
dm_spi->max_hz = fdtdec_get_int(gd->fdt_blob, bus->of_offset,
"spi-max-frequency", 250000000);
/* get clock rate */
ret = clk_get_by_index(bus, 0, &clkdev);
if (ret < 0) {
printf("pic32-spi: error, clk not found\n");
return ret;
}
priv->clk_rate = clk_get_periph_rate(clkdev, ret);
/* initialize HW */
pic32_spi_hw_init(priv);
/* set word len */
pic32_spi_set_word_size(priv, SPI_DEFAULT_WORDLEN);
/* PIC32 SPI controller can automatically drive /CS during transfer
* depending on fifo fill-level. /CS will stay asserted as long as
* TX fifo is non-empty, else will be deasserted confirming completion
* of the ongoing transfer. To avoid this sort of error we will drive
* /CS manually by toggling cs-gpio pins.
*/
ret = gpio_request_by_name_nodev(gd->fdt_blob, bus->of_offset,
"cs-gpios", 0,
&priv->cs_gpio, GPIOD_IS_OUT);
if (ret) {
printf("pic32-spi: error, cs-gpios not found\n");
return ret;
}
return 0;
}
static int pic32_eth_probe(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_platdata(dev);
struct pic32eth_dev *priv = dev_get_priv(dev);
const char *phy_mode;
void __iomem *iobase;
fdt_addr_t addr;
fdt_size_t size;
int offset = 0;
int phy_addr = -1;
addr = fdtdec_get_addr_size(gd->fdt_blob, dev_of_offset(dev), "reg",
&size);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
iobase = ioremap(addr, size);
pdata->iobase = (phys_addr_t)addr;
/* get phy mode */
pdata->phy_interface = -1;
phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
NULL);
if (phy_mode)
pdata->phy_interface = phy_get_interface_by_name(phy_mode);
if (pdata->phy_interface == -1) {
debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
return -EINVAL;
}
/* get phy addr */
offset = fdtdec_lookup_phandle(gd->fdt_blob, dev_of_offset(dev),
"phy-handle");
if (offset > 0)
phy_addr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1);
/* phy reset gpio */
gpio_request_by_name_nodev(dev_ofnode(dev), "reset-gpios", 0,
&priv->rst_gpio, GPIOD_IS_OUT);
priv->phyif = pdata->phy_interface;
priv->phy_addr = phy_addr;
priv->ectl_regs = iobase;
priv->emac_regs = iobase + PIC32_EMAC1CFG1;
pic32_mii_init(priv);
return pic32_phy_init(priv, dev);
}
int uniphier_pinctrl_probe(struct udevice *dev,
struct uniphier_pinctrl_socdata *socdata)
{
struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
fdt_addr_t addr;
fdt_size_t size;
addr = fdtdec_get_addr_size(gd->fdt_blob, dev->of_offset, "reg",
&size);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
priv->base = map_sysmem(addr, size);
if (!priv->base)
return -ENOMEM;
priv->socdata = socdata;
return 0;
}
fdt_addr_t fdtdec_get_addr(const void *blob, int node,
const char *prop_name)
{
return fdtdec_get_addr_size(blob, node, prop_name, NULL);
}
