gen_table *
make_gen_tables (insn_table *isa, decode_table *rules)
{
gen_table *gen = ZALLOC (gen_table);
gen->isa = isa;
gen->rules = rules;
if (options.gen.multi_sim)
{
gen_list **last = &gen->tables;
model_entry *model;
filter *processors;
if (options.model_filter != NULL)
processors = options.model_filter;
else
processors = isa->model->processors;
for (model = isa->model->models; model != NULL; model = model->next)
{
if (filter_is_member (processors, model->name))
{
*last = make_table (isa, rules, model);
last = &(*last)->next;
}
}
}
else
{
gen->tables = make_table (isa, rules, NULL);
}
return gen;
}
static void
itable_print_set (lf *file, filter *set, filter *members)
{
char *elem;
lf_printf (file, "\"");
elem = filter_next (members, "");
if (elem != NULL)
{
while (1)
{
lf_printf (file, "%s", elem);
elem = filter_next (members, elem);
if (elem == NULL)
break;
lf_printf (file, ",");
}
}
lf_printf (file, "\",\n");
lf_printf (file, "{");
for (elem = filter_next (set, "");
elem != NULL; elem = filter_next (set, elem))
{
if (filter_is_member (members, elem))
{
lf_printf (file, " 1,");
}
else
{
lf_printf (file, " 0,");
}
}
/* always print a dummy element, to avoid empty initializers. */
lf_printf (file, " 99 },\n");
}
static gen_list *
make_table (insn_table *isa, decode_table *rules, model_entry *model)
{
insn_entry *insn;
gen_list *entry = ZALLOC (gen_list);
entry->table = ZALLOC (gen_entry);
entry->table->top = entry;
entry->model = model;
entry->isa = isa;
for (insn = isa->insns; insn != NULL; insn = insn->next)
{
if (model == NULL
|| insn->processors == NULL
|| filter_is_member (insn->processors, model->name))
{
insn_list_insert (&entry->table->insns, &entry->table->nr_insns, insn, NULL, /* expanded_bits - none yet */
NULL, /* opcodes - none yet */
0, /* nr_prefetched_words - none yet */
report_duplicate_insns);
}
}
entry->table->opcode_rule = rules;
return entry;
}
void
print_semantic_body (lf *file,
insn_entry * instruction,
opcode_bits *expanded_bits, insn_opcodes *opcodes)
{
/* validate the instruction, if a cache this has already been done */
if (!options.gen.icache)
{
print_idecode_validate (file, instruction, opcodes);
}
print_itrace (file, instruction, 0 /*put_value_in_cache */ );
/* generate the instruction profile call - this is delayed until
after the instruction has been verified. The count macro
generated is prefixed by ITABLE_PREFIX */
{
lf_printf (file, "\n");
lf_indent_suppress (file);
lf_printf (file, "#if defined (%sPROFILE_COUNT_INSN)\n",
options.module.itable.prefix.u);
lf_printf (file, "%sPROFILE_COUNT_INSN (CPU, CIA, MY_INDEX);\n",
options.module.itable.prefix.u);
lf_indent_suppress (file);
lf_printf (file, "#endif\n");
}
/* generate the model call - this is delayed until after the
instruction has been verified */
{
lf_printf (file, "\n");
lf_indent_suppress (file);
lf_printf (file, "#if defined (WITH_MON)\n");
lf_printf (file, "/* monitoring: */\n");
lf_printf (file, "if (WITH_MON & MONITOR_INSTRUCTION_ISSUE)\n");
lf_printf (file, " mon_issue (");
print_function_name (file,
instruction->name,
instruction->format_name,
NULL, NULL, function_name_prefix_itable);
lf_printf (file, ", cpu, cia);\n");
lf_indent_suppress (file);
lf_printf (file, "#endif\n");
lf_printf (file, "\n");
}
/* determine the new instruction address */
{
lf_printf (file, "/* keep the next instruction address handy */\n");
if (options.gen.nia == nia_is_invalid)
{
lf_printf (file, "nia = %sINVALID_INSTRUCTION_ADDRESS;\n",
options.module.global.prefix.u);
}
else
{
int nr_immeds = instruction->nr_words - 1;
if (options.gen.delayed_branch)
{
if (nr_immeds > 0)
{
lf_printf (file, "cia.dp += %d * %d; %s\n",
options.insn_bit_size / 8, nr_immeds,
"/* skip dp immeds */");
}
lf_printf (file, "nia.ip = cia.dp; %s\n",
"/* instruction pointer */");
lf_printf (file, "nia.dp = cia.dp + %d; %s\n",
options.insn_bit_size / 8,
"/* delayed-slot pointer */");
}
else
{
if (nr_immeds > 0)
{
lf_printf (file, "nia = cia + %d * (%d + 1); %s\n",
options.insn_bit_size / 8, nr_immeds,
"/* skip immeds as well */");
}
else
{
lf_printf (file, "nia = cia + %d;\n",
options.insn_bit_size / 8);
}
}
}
}
/* if conditional, generate code to verify that the instruction
should be issued */
if (filter_is_member (instruction->options, "c")
|| options.gen.conditional_issue)
{
lf_printf (file, "\n");
lf_printf (file, "/* execute only if conditional passes */\n");
lf_printf (file, "if (IS_CONDITION_OK)\n");
lf_printf (file, " {\n");
lf_indent (file, +4);
/* FIXME - need to log a conditional failure */
}
/* Architecture expects a REG to be zero. Instead of having to
check every read to see if it is refering to that REG just zap it
at the start of every instruction */
if (options.gen.zero_reg)
{
lf_printf (file, "\n");
lf_printf (file, "/* Architecture expects REG to be zero */\n");
lf_printf (file, "GPR_CLEAR(%d);\n", options.gen.zero_reg_nr);
}
/* generate the code (or at least something */
lf_printf (file, "\n");
lf_printf (file, "/* semantics: */\n");
if (instruction->code != NULL)
{
/* true code */
lf_printf (file, "{\n");
lf_indent (file, +2);
lf_print__line_ref (file, instruction->code->line);
table_print_code (file, instruction->code);
lf_indent (file, -2);
lf_printf (file, "}\n");
lf_print__internal_ref (file);
}
else if (filter_is_member (instruction->options, "nop"))
{
lf_print__internal_ref (file);
}
else
{
const char *prefix = "sim_engine_abort (";
int indent = strlen (prefix);
/* abort so it is implemented now */
lf_print__line_ref (file, instruction->line);
lf_printf (file, "%sSD, CPU, cia, \\\n", prefix);
lf_indent (file, +indent);
lf_printf (file, "\"%s:%d:0x%%08lx:%%s unimplemented\\n\", \\\n",
filter_filename (instruction->line->file_name),
instruction->line->line_nr);
lf_printf (file, "(long) CIA, \\\n");
lf_printf (file, "%sitable[MY_INDEX].name);\n",
options.module.itable.prefix.l);
lf_indent (file, -indent);
lf_print__internal_ref (file);
}
/* Close off the conditional execution */
if (filter_is_member (instruction->options, "c")
|| options.gen.conditional_issue)
{
lf_indent (file, -4);
lf_printf (file, " }\n");
}
}
void
print_icache_body (lf *file,
insn_entry * instruction,
opcode_bits *expanded_bits,
cache_entry *cache_rules,
icache_decl_type what_to_declare,
icache_body_type what_to_do, int nr_prefetched_words)
{
/* extract instruction fields */
lf_printf (file, "/* Extraction: %s\n", instruction->name);
lf_printf (file, " ");
switch (what_to_declare)
{
case define_variables:
lf_printf (file, "#define");
break;
case declare_variables:
lf_printf (file, "declare");
break;
case undef_variables:
lf_printf (file, "#undef");
break;
}
lf_printf (file, " ");
switch (what_to_do)
{
case get_values_from_icache:
lf_printf (file, "get-values-from-icache");
break;
case put_values_in_icache:
lf_printf (file, "put-values-in-icache");
break;
case both_values_and_icache:
lf_printf (file, "get-values-from-icache|put-values-in-icache");
break;
case do_not_use_icache:
lf_printf (file, "do-not-use-icache");
break;
}
lf_printf (file, "\n ");
print_insn_words (file, instruction);
lf_printf (file, " */\n");
/* pass zero - fetch from memory any missing instructions.
Some of the instructions will have already been fetched (in the
instruction array), others will still need fetching. */
switch (what_to_do)
{
case get_values_from_icache:
break;
case put_values_in_icache:
case both_values_and_icache:
case do_not_use_icache:
{
int word_nr;
switch (what_to_declare)
{
case undef_variables:
break;
case define_variables:
case declare_variables:
for (word_nr = nr_prefetched_words;
word_nr < instruction->nr_words; word_nr++)
{
/* FIXME - should be using print_icache_extraction? */
lf_printf (file,
"%sinstruction_word instruction_%d UNUSED = ",
options.module.global.prefix.l, word_nr);
lf_printf (file, "IMEM%d_IMMED (cia, %d)",
options.insn_bit_size, word_nr);
lf_printf (file, ";\n");
}
}
}
}
/* if putting the instruction words in the cache, define references
for them */
if (options.gen.insn_in_icache)
{
/* FIXME: is the instruction_word type correct? */
print_icache_extraction (file, instruction->format_name, cache_value, "insn", /* name */
"instruction_word", /* type */
"instruction", /* expression */
NULL, /* origin */
NULL, /* line */
NULL, NULL, what_to_declare, what_to_do);
}
lf_printf (file, "\n");
/* pass one - process instruction fields.
If there is no cache rule, the default is to enter the field into
the cache */
{
insn_word_entry *word;
for (word = instruction->words; word != NULL; word = word->next)
{
insn_field_entry *cur_field;
for (cur_field = word->first;
cur_field->first < options.insn_bit_size;
cur_field = cur_field->next)
{
/* Always expand named fields (even if constant), so
references are valid. */
if (cur_field->type == insn_field_string)
{
cache_entry *cache_rule;
cache_entry_type value_type = cache_value;
line_ref *value_line = instruction->line;
/* check the cache table to see if it contains a rule
overriding the default cache action for an
instruction field */
for (cache_rule = cache_rules;
cache_rule != NULL; cache_rule = cache_rule->next)
{
if (filter_is_subset (instruction->field_names,
cache_rule->original_fields)
&& strcmp (cache_rule->name,
cur_field->val_string) == 0)
{
value_type = cache_rule->entry_type;
value_line = cache_rule->line;
if (value_type == compute_value)
{
options.warning (cache_rule->line,
"instruction field of type `compute' changed to `cache'\n");
cache_rule->entry_type = cache_value;
}
break;
}
}
/* Define an entry for the field within the
instruction */
print_icache_extraction (file, instruction->format_name, value_type, cur_field->val_string, /* name */
NULL, /* type */
NULL, /* expression */
cur_field->val_string, /* insn field */
value_line,
cur_field,
expanded_bits,
what_to_declare, what_to_do);
}
}
}
}
/* pass two - any cache fields not processed above */
{
cache_entry *cache_rule;
for (cache_rule = cache_rules;
cache_rule != NULL; cache_rule = cache_rule->next)
{
if (filter_is_subset (instruction->field_names,
cache_rule->original_fields)
&& !filter_is_member (instruction->field_names, cache_rule->name))
{
char *single_field =
filter_next (cache_rule->original_fields, "");
if (filter_next (cache_rule->original_fields, single_field) !=
NULL)
single_field = NULL;
print_icache_extraction (file, instruction->format_name, cache_rule->entry_type, cache_rule->name, cache_rule->type, cache_rule->expression, single_field, cache_rule->line, NULL, /* cur_field */
expanded_bits,
what_to_declare, what_to_do);
}
}
}
lf_print__internal_ref (file);
}
/* Is the bit, according to the decode rule, identical across all the
instructions? */
static int
insns_bit_useless (insn_list *insns, decode_table *rule, int bit_nr)
{
insn_list *entry;
int value = -1;
int is_useless = 1; /* cleared if something actually found */
/* check the instructions for some constant value in at least one of
the bit fields */
for (entry = insns; entry != NULL; entry = entry->next)
{
insn_word_entry *word = entry->insn->word[rule->word_nr];
insn_bit_entry *bit = word->bit[bit_nr];
switch (bit->field->type)
{
case insn_field_invalid:
ASSERT (0);
break;
case insn_field_wild:
case insn_field_reserved:
/* neither useless or useful - ignore */
break;
case insn_field_int:
switch (rule->search)
{
case decode_find_strings:
/* an integer isn't a string */
return 1;
case decode_find_constants:
case decode_find_mixed:
/* an integer is useful if its value isn't the same
between all instructions. The first time through the
value is saved, the second time through (if the
values differ) it is marked as useful. */
if (value < 0)
value = bit->value;
else if (value != bit->value)
is_useless = 0;
break;
}
break;
case insn_field_string:
switch (rule->search)
{
case decode_find_strings:
/* at least one string, keep checking */
is_useless = 0;
break;
case decode_find_constants:
case decode_find_mixed:
if (filter_is_member (rule->constant_field_names,
bit->field->val_string))
/* a string field forced to constant? */
is_useless = 0;
else if (bit->field->conditions != NULL
&& bit->field->conditions->test == insn_field_cond_eq
&& bit->field->conditions->type == insn_field_cond_value)
{
int shift = bit->field->last - bit_nr;
int bitvalue = (bit->field->conditions->value >> shift) & 1;
if (value < 0)
value = bitvalue;
else if (value != bitvalue)
is_useless = 0;
}
else if (rule->search == decode_find_constants)
/* the string field isn't constant */
return 1;
break;
}
}
int
main (int argc,
char **argv,
char **envp)
{
cache_entry *cache_rules = NULL;
lf_file_references file_references = lf_include_references;
decode_table *decode_rules = NULL;
insn_table *isa = NULL;
gen_table *gen = NULL;
char *real_file_name = NULL;
int is_header = 0;
int ch;
lf *standard_out = lf_open ("-", "stdout", lf_omit_references, lf_is_text, "igen");
INIT_OPTIONS ();
if (argc == 1)
{
printf ("Usage:\n");
printf ("\n");
printf (" igen <config-opts> ... <input-opts>... <output-opts>...\n");
printf ("\n");
printf ("Config options:\n");
printf ("\n");
printf (" -B <bit-size>\n");
printf ("\t Set the number of bits in an instruction (depreciated).\n");
printf ("\t This option can now be set directly in the instruction table.\n");
printf ("\n");
printf (" -D <data-structure>\n");
printf ("\t Dump the specified data structure to stdout. Valid structures include:\n");
printf ("\t processor-names - list the names of all the processors (models)\n");
printf ("\n");
printf (" -F <filter-list>\n");
printf ("\t Filter out any instructions with a non-empty flags field that contains\n");
printf ("\t a flag not listed in the <filter-list>.\n");
printf ("\n");
printf (" -H <high-bit>\n");
printf ("\t Set the number of the high (most significant) instruction bit (depreciated).\n");
printf ("\t This option can now be set directly in the instruction table.\n");
printf ("\n");
printf (" -I <directory>\n");
printf ("\t Add <directory> to the list of directories searched when opening a file\n");
printf ("\n");
printf (" -M <model-list>\n");
printf ("\t Filter out any instructions that do not support at least one of the listed\n");
printf ("\t models (An instructions with no model information is considered to support\n");
printf ("\t all models.).\n");
printf ("\n");
printf (" -N <nr-cpus>\n");
printf ("\t Generate a simulator supporting <nr-cpus>\n");
printf ("\t Specify `-N 0' to disable generation of the SMP. Specifying `-N 1' will\n");
printf ("\t still generate an SMP enabled simulator but will only support one CPU.\n");
printf ("\n");
printf (" -T <mechanism>\n");
printf ("\t Override the decode mechanism specified by the decode rules\n");
printf ("\n");
printf (" -P <prefix>\n");
printf ("\t Prepend global names (except itable) with the string <prefix>.\n");
printf ("\t Specify -P <module>=<prefix> to set a specific <module>'s prefix.\n");
printf ("\n");
printf (" -S <suffix>\n");
printf ("\t Replace a global name (suffix) (except itable) with the string <suffix>.\n");
printf ("\t Specify -S <module>=<suffix> to change a specific <module>'s name (suffix).\n");
printf ("\n");
printf (" -Werror\n");
printf ("\t Make warnings errors\n");
printf (" -Wnodiscard\n");
printf ("\t Suppress warnings about discarded functions and instructions\n");
printf (" -Wnowidth\n");
printf ("\t Suppress warnings about instructions with invalid widths\n");
printf (" -Wnounimplemented\n");
printf ("\t Suppress warnings about unimplemented instructions\n");
printf ("\n");
printf (" -G [!]<gen-option>\n");
printf ("\t Any of the following options:\n");
printf ("\n");
printf ("\t decode-duplicate - Override the decode rules, forcing the duplication of\n");
printf ("\t semantic functions\n");
printf ("\t decode-combine - Combine any duplicated entries within a table\n");
printf ("\t decode-zero-reserved - Override the decode rules, forcing reserved bits to be\n");
printf ("\t treated as zero.\n");
printf ("\t decode-switch-is-goto - Overfide the padded-switch code type as a goto-switch\n");
printf ("\n");
printf ("\t gen-conditional-issue - conditionally issue each instruction\n");
printf ("\t gen-delayed-branch - need both cia and nia passed around\n");
printf ("\t gen-direct-access - use #defines to directly access values\n");
printf ("\t gen-zero-r<N> - arch assumes GPR(<N>) == 0, keep it that way\n");
printf ("\t gen-icache[=<N> - generate an instruction cracking cache of size <N>\n");
printf ("\t Default size is %d\n", options.gen.icache_size);
printf ("\t gen-insn-in-icache - save original instruction when cracking\n");
printf ("\t gen-multi-sim[=MODEL] - generate multiple simulators - one per model\n");
printf ("\t If specified MODEL is made the default architecture.\n");
printf ("\t By default, a single simulator that will\n");
printf ("\t execute any instruction is generated\n");
printf ("\t gen-multi-word - generate code allowing for multi-word insns\n");
printf ("\t gen-semantic-icache - include semantic code in cracking functions\n");
printf ("\t gen-slot-verification - perform slot verification as part of decode\n");
printf ("\t gen-nia-invalid - NIA defaults to nia_invalid\n");
printf ("\t gen-nia-void - do not compute/return NIA\n");
printf ("\n");
printf ("\t trace-combine - report combined entries a rule application\n");
printf ("\t trace-entries - report entries after a rules application\n");
printf ("\t trace-rule-rejection - report each rule as rejected\n");
printf ("\t trace-rule-selection - report each rule as selected\n");
printf ("\t trace-insn-insertion - report each instruction as it is inserted into a decode table\n");
printf ("\t trace-rule-expansion - report each instruction as it is expanded (before insertion into a decode table)\n");
printf ("\t trace-all - enable all trace options\n");
printf ("\n");
printf ("\t field-widths - instruction formats specify widths (depreciated)\n");
printf ("\t By default, an instruction format specifies bit\n");
printf ("\t positions\n");
printf ("\t This option can now be set directly in the\n");
printf ("\t instruction table\n");
printf ("\t jumps - use jumps instead of function calls\n");
printf ("\t omit-line-numbers - do not include line number information in the output\n");
printf ("\n");
printf ("Input options:\n");
printf ("\n");
printf (" -k <cache-rules> (depreciated)\n");
printf (" -o <decode-rules>\n");
printf (" -i <instruction-table>\n");
printf ("\n");
printf ("Output options:\n");
printf ("\n");
printf (" -x Perform expansion (required)\n");
printf (" -n <real-name> Specify the real name of the next output file\n");
printf (" -h Generate the header (.h) file rather than the body (.c)\n");
printf (" -c <output-file> output icache\n");
printf (" -d <output-file> output idecode\n");
printf (" -e <output-file> output engine\n");
printf (" -f <output-file> output support functions\n");
printf (" -m <output-file> output model\n");
printf (" -r <output-file> output multi-sim run\n");
printf (" -s <output-file> output schematic\n");
printf (" -t <output-file> output itable\n");
}
while ((ch = getopt(argc, argv,
"B:D:F:G:H:I:M:N:P:T:W:o:k:i:n:hc:d:e:m:r:s:t:f:x"))
!= -1)
{
fprintf (stderr, " -%c ", ch);
if (optarg)
fprintf (stderr, "%s ", optarg);
fprintf (stderr, "\\\n");
switch(ch)
{
case 'M':
filter_parse (&options.model_filter, optarg);
break;
case 'D':
if (strcmp (optarg, "processor-names"))
{
char *processor;
for (processor = filter_next (options.model_filter, "");
processor != NULL;
processor = filter_next (options.model_filter, processor))
lf_printf (standard_out, "%s\n", processor);
}
else
error (NULL, "Unknown data structure %s, not dumped\n", optarg);
break;
case 'F':
filter_parse (&options.flags_filter, optarg);
break;
case 'I':
{
table_include **dir = &options.include;
while ((*dir) != NULL)
dir = &(*dir)->next;
(*dir) = ZALLOC (table_include);
(*dir)->dir = strdup (optarg);
}
break;
case 'B':
options.insn_bit_size = a2i (optarg);
if (options.insn_bit_size <= 0
|| options.insn_bit_size > max_insn_bit_size)
{
error (NULL, "Instruction bitsize must be in range 1..%d\n",
max_insn_bit_size);
}
if (options.hi_bit_nr != options.insn_bit_size - 1
&& options.hi_bit_nr != 0)
{
error (NULL, "Conflict betweem hi-bit-nr and insn-bit-size\n");
}
break;
case 'H':
options.hi_bit_nr = a2i (optarg);
if (options.hi_bit_nr != options.insn_bit_size - 1
&& options.hi_bit_nr != 0)
{
error (NULL, "Conflict between hi-bit-nr and insn-bit-size\n");
}
break;
case 'N':
options.gen.smp = a2i (optarg);
break;
case 'P':
case 'S':
{
igen_module *names;
igen_name *name;
char *chp;
chp = strchr (optarg, '=');
if (chp == NULL)
{
names = &options.module.global;
chp = optarg;
}
else
{
chp = chp + 1; /* skip `=' */
names = NULL;
if (strncmp (optarg, "global=", chp - optarg) == 0)
{
names = &options.module.global;
}
if (strncmp (optarg, "engine=", chp - optarg) == 0)
{
names = &options.module.engine;
}
if (strncmp (optarg, "icache=", chp - optarg) == 0)
{
names = &options.module.icache;
}
if (strncmp (optarg, "idecode=", chp - optarg) == 0)
{
names = &options.module.idecode;
}
if (strncmp (optarg, "itable=", chp - optarg) == 0)
{
names = &options.module.itable;
}
if (strncmp (optarg, "semantics=", chp - optarg) == 0)
{
names = &options.module.semantics;
}
if (strncmp (optarg, "support=", chp - optarg) == 0)
{
names = &options.module.support;
}
if (names == NULL)
{
error (NULL, "Prefix `%s' unreconized\n", optarg);
}
}
switch (ch)
{
case 'P':
name = &names->prefix;
break;
case 'S':
name = &names->suffix;
break;
}
name->u = strdup (chp);
name->l = strdup (chp);
chp = name->u;
while (*chp) {
if (islower(*chp))
*chp = toupper(*chp);
chp++;
}
if (name == &options.module.global.prefix)
{
options.module.engine.prefix = options.module.global.prefix;
options.module.icache.prefix = options.module.global.prefix;
options.module.idecode.prefix = options.module.global.prefix;
/* options.module.itable.prefix = options.module.global.prefix; */
options.module.semantics.prefix = options.module.global.prefix;
options.module.support.prefix = options.module.global.prefix;
}
if (name == &options.module.global.suffix)
{
options.module.engine.suffix = options.module.global.suffix;
options.module.icache.suffix = options.module.global.suffix;
options.module.idecode.suffix = options.module.global.suffix;
/* options.module.itable.suffix = options.module.global.suffix; */
options.module.semantics.suffix = options.module.global.suffix;
options.module.support.suffix = options.module.global.suffix;
}
break;
}
case 'W':
{
if (strcmp (optarg, "error") == 0)
options.warning = error;
else if (strcmp (optarg, "nodiscard") == 0)
options.warn.discard = 0;
else if (strcmp (optarg, "discard") == 0)
options.warn.discard = 1;
else if (strcmp (optarg, "nowidth") == 0)
options.warn.width = 0;
else if (strcmp (optarg, "width") == 0)
options.warn.width = 1;
else if (strcmp (optarg, "nounimplemented") == 0)
options.warn.unimplemented = 0;
else if (strcmp (optarg, "unimplemented") == 0)
options.warn.unimplemented = 1;
else
error (NULL, "Unknown -W argument `%s'\n", optarg);
break;
}
case 'G':
{
int enable_p;
char *argp;
if (strncmp (optarg, "no-", strlen ("no-")) == 0)
{
argp = optarg + strlen ("no-");
enable_p = 0;
}
else if (strncmp (optarg, "!", strlen ("!")) == 0)
{
argp = optarg + strlen ("no-");
enable_p = 0;
}
else
{
argp = optarg;
enable_p = 1;
}
if (strcmp (argp, "decode-duplicate") == 0)
{
options.decode.duplicate = enable_p;
}
else if (strcmp (argp, "decode-combine") == 0)
{
options.decode.combine = enable_p;
}
else if (strcmp (argp, "decode-zero-reserved") == 0)
{
options.decode.zero_reserved = enable_p;
}
else if (strcmp (argp, "gen-conditional-issue") == 0)
{
options.gen.conditional_issue = enable_p;
}
else if (strcmp (argp, "conditional-issue") == 0)
{
options.gen.conditional_issue = enable_p;
options.warning (NULL, "Option conditional-issue replaced by gen-conditional-issue\n");
}
else if (strcmp (argp, "gen-delayed-branch") == 0)
{
options.gen.delayed_branch = enable_p;
}
else if (strcmp (argp, "delayed-branch") == 0)
{
options.gen.delayed_branch = enable_p;
options.warning (NULL, "Option delayed-branch replaced by gen-delayed-branch\n");
}
else if (strcmp (argp, "gen-direct-access") == 0)
{
options.gen.direct_access = enable_p;
}
else if (strcmp (argp, "direct-access") == 0)
{
options.gen.direct_access = enable_p;
options.warning (NULL, "Option direct-access replaced by gen-direct-access\n");
}
else if (strncmp (argp, "gen-zero-r", strlen ("gen-zero-r")) == 0)
{
options.gen.zero_reg = enable_p;
options.gen.zero_reg_nr = atoi (argp + strlen ("gen-zero-r"));
}
else if (strncmp (argp, "zero-r", strlen ("zero-r")) == 0)
{
options.gen.zero_reg = enable_p;
options.gen.zero_reg_nr = atoi (argp + strlen ("zero-r"));
options.warning (NULL, "Option zero-r<N> replaced by gen-zero-r<N>\n");
}
else if (strncmp (argp, "gen-icache", strlen ("gen-icache")) == 0)
{
switch (argp[strlen ("gen-icache")])
{
case '=':
options.gen.icache_size = atoi (argp + strlen ("gen-icache") + 1);
options.gen.icache = enable_p;
break;
case '\0':
options.gen.icache = enable_p;
break;
default:
error (NULL, "Expecting -Ggen-icache or -Ggen-icache=<N>\n");
}
}
else if (strcmp (argp, "gen-insn-in-icache") == 0)
{
options.gen.insn_in_icache = enable_p;
}
else if (strncmp (argp, "gen-multi-sim", strlen ("gen-multi-sim")) == 0)
{
char *arg = &argp[strlen ("gen-multi-sim")];
switch (arg[0])
{
case '=':
options.gen.multi_sim = enable_p;
options.gen.default_model = arg + 1;
if (! filter_is_member (options.model_filter, options.gen.default_model))
error (NULL, "multi-sim model %s unknown\n", options.gen.default_model);
break;
case '\0':
options.gen.multi_sim = enable_p;
options.gen.default_model = NULL;
break;
default:
error (NULL, "Expecting -Ggen-multi-sim or -Ggen-multi-sim=<MODEL>\n");
break;
}
}
else if (strcmp (argp, "gen-multi-word") == 0)
{
options.gen.multi_word = enable_p;
}
else if (strcmp (argp, "gen-semantic-icache") == 0)
{
options.gen.semantic_icache = enable_p;
}
else if (strcmp (argp, "gen-slot-verification") == 0)
{
options.gen.slot_verification = enable_p;
}
else if (strcmp (argp, "verify-slot") == 0)
{
options.gen.slot_verification = enable_p;
options.warning (NULL, "Option verify-slot replaced by gen-slot-verification\n");
}
else if (strcmp (argp, "gen-nia-invalid") == 0)
{
options.gen.nia = nia_is_invalid;
}
else if (strcmp (argp, "default-nia-minus-one") == 0)
{
options.gen.nia = nia_is_invalid;
options.warning (NULL, "Option default-nia-minus-one replaced by gen-nia-invalid\n");
}
else if (strcmp (argp, "gen-nia-void") == 0)
{
options.gen.nia = nia_is_void;
}
else if (strcmp (argp, "trace-all") == 0)
{
memset (&options.trace, enable_p, sizeof (options.trace));
}
else if (strcmp (argp, "trace-combine") == 0)
{
options.trace.combine = enable_p;
}
else if (strcmp (argp, "trace-entries") == 0)
{
options.trace.entries = enable_p;
}
else if (strcmp (argp, "trace-rule-rejection") == 0)
{
options.trace.rule_rejection = enable_p;
}
else if (strcmp (argp, "trace-rule-selection") == 0)
{
options.trace.rule_selection = enable_p;
}
else if (strcmp (argp, "trace-insn-insertion") == 0)
{
options.trace.insn_insertion = enable_p;
}
else if (strcmp (argp, "trace-insn-expansion") == 0)
{
options.trace.insn_expansion = enable_p;
}
else if (strcmp (argp, "jumps") == 0)
{
options.gen.code = generate_jumps;
}
else if (strcmp (argp, "field-widths") == 0)
{
options.insn_specifying_widths = enable_p;
}
else if (strcmp (argp, "omit-line-numbers") == 0)
{
file_references = lf_omit_references;
}
else
{
error (NULL, "Unknown option %s\n", optarg);
}
break;
}
case 'i':
isa = load_insn_table (optarg, cache_rules);
if (isa->illegal_insn == NULL)
error (NULL, "illegal-instruction missing from insn table\n");
break;
case 'x':
gen = do_gen (isa, decode_rules);
break;
case 'o':
decode_rules = load_decode_table (optarg);
break;
case 'k':
if (isa != NULL)
error (NULL, "Cache file must appear before the insn file\n");
cache_rules = load_cache_table (optarg);
break;
case 'n':
real_file_name = strdup(optarg);
break;
case 'h':
is_header = 1;
break;
case 'c':
case 'd':
case 'e':
case 'f':
case 'm':
case 'r':
case 's':
case 't':
{
lf *file = lf_open(optarg, real_file_name, file_references,
(is_header ? lf_is_h : lf_is_c),
argv[0]);
if (gen == NULL && ch != 't' && ch != 'm' && ch != 'f')
{
options.warning (NULL, "Explicitly generate tables with -x option\n");
gen = do_gen (isa, decode_rules);
}
lf_print__file_start(file);
switch (ch)
{
case 'm':
if (is_header)
gen_model_h (file, isa);
else
gen_model_c (file, isa);
break;
case 't':
if (is_header)
gen_itable_h (file, isa);
else
gen_itable_c (file, isa);
break;
case 'f':
if (is_header)
gen_support_h (file, isa);
else
gen_support_c (file, isa);
break;
case 'r':
if (is_header)
options.warning (NULL, "-hr option ignored\n");
else
gen_run_c (file, gen);
break;
case 's':
if(is_header)
gen_semantics_h (file, gen->semantics, isa->max_nr_words);
else
gen_semantics_c (file, gen->semantics, isa->caches);
break;
case 'd':
if (is_header)
gen_idecode_h (file, gen, isa, cache_rules);
else
gen_idecode_c (file, gen, isa, cache_rules);
break;
case 'e':
if (is_header)
gen_engine_h (file, gen, isa, cache_rules);
else
gen_engine_c (file, gen, isa, cache_rules);
break;
case 'c':
if (is_header)
gen_icache_h (file,
gen->semantics,
isa->functions,
isa->max_nr_words);
else
gen_icache_c (file,
gen->semantics,
isa->functions,
cache_rules);
break;
}
lf_print__file_finish(file);
lf_close(file);
is_header = 0;
}
real_file_name = NULL;
break;
default:
ERROR ("Bad switch");
}
}
return (0);
}
