示例#1
0
int __init omap4_pm_init_opp_table(void)
{
    struct omap_opp_def *opp_def;
    struct device *dev;
    struct clk *gpu_fclk;
    int i, r;

    /*
     * Allow multiple calls, but initialize only if not already initalized
     * even if the previous call failed, coz, no reason we'd succeed again
     */
    if (omap4_table_init)
        return 0;
    omap4_table_init = 1;

    if (omap_rev() <= OMAP4430_REV_ES2_0)
        opp_def = omap44xx_pre_es2_1_opp_def_list;
    else
        opp_def = omap44xx_opp_def_list;

    for (i = 0; i < omap44xx_opp_def_size; i++) {
        r = opp_add(opp_def);
        if (r)
            pr_err("unable to add OPP %ld Hz for %s\n",
                   opp_def->freq, opp_def->hwmod_name);
        opp_def++;
    }

    dpll_mpu_clk = clk_get(NULL, "dpll_mpu_ck");
    iva_clk = clk_get(NULL, "dpll_iva_m5x2_ck");
    dsp_clk = clk_get(NULL, "dpll_iva_m4x2_ck");
    l3_clk = clk_get(NULL, "dpll_core_m5x2_ck");
    core_m2_clk = clk_get(NULL, "dpll_core_m2_ck");
    core_m3_clk = clk_get(NULL, "dpll_core_m3x2_ck");
    core_m6_clk = clk_get(NULL, "dpll_core_m6x2_ck");
    core_m7_clk = clk_get(NULL, "dpll_core_m7x2_ck");
    sgx_clk = clk_get(NULL, "dpll_per_m7x2_ck");
    gpu_fclk = clk_get(NULL, "gpu_fck");
    per_m3_clk = clk_get(NULL, "dpll_per_m3x2_ck");
    per_m6_clk = clk_get(NULL, "dpll_per_m6x2_ck");
    abe_clk = clk_get(NULL, "abe_clk");
    fdif_clk = clk_get(NULL, "fdif_fck");
    hsi_clk = clk_get(NULL, "hsi_fck");

    /* Set SGX parent to PER DPLL */
    clk_set_parent(gpu_fclk, sgx_clk);
    clk_put(gpu_fclk);

    /* Populate the set rate and get rate for mpu, iva, dsp and l3 device */
    dev = omap2_get_mpuss_device();
    if (dev)
        opp_populate_rate_fns(dev, omap4_mpu_set_rate,
                              omap4_mpu_get_rate);

    dev = omap2_get_iva_device();
    if (dev)
        opp_populate_rate_fns(dev, omap4_iva_set_rate,
                              omap4_iva_get_rate);

    dev = omap4_get_dsp_device();
    if (dev)
        opp_populate_rate_fns(dev, omap4_iva_set_rate,
                              omap4_iva_get_rate);

    dev = omap2_get_l3_device();
    if (dev)
        opp_populate_rate_fns(dev, omap4_l3_set_rate,
                              omap4_l3_get_rate);

    /*
     * This is a temporary hack since emif clocks cannot be scaled
     * on ES1.0 and ES2.0. Once everybody has migrated to ES2.1 this
     * check can be remove.
     */
    if (omap_rev() > OMAP4430_REV_ES2_0) {
        dev = find_dev_ptr("emif1");
        if (dev)
            opp_populate_rate_fns(dev, omap4_emif_set_rate,
                                  omap4_emif_get_rate);

        dev = find_dev_ptr("emif2");
        if (dev)
            opp_populate_rate_fns(dev, omap4_emif_set_rate,
                                  omap4_emif_get_rate);
    }

    dev = find_dev_ptr("omap-aess-audio");
    if (dev)
        opp_populate_rate_fns(dev, omap4_abe_set_rate,
                              omap4_abe_get_rate);

    dev = find_dev_ptr("gpu");
    if (dev)
        opp_populate_rate_fns(dev, omap4_sgx_set_rate,
                              omap4_sgx_get_rate);

    dev = find_dev_ptr("fdif");
    if (dev)
        opp_populate_rate_fns(dev, omap4_fdif_set_rate,
                              omap4_fdif_get_rate);

    dev = find_dev_ptr("hsi");
    if (dev)
        opp_populate_rate_fns(dev, omap4_hsi_set_rate,
                              omap4_hsi_get_rate);

    return 0;
}
示例#2
0
int __init omap4_pm_init_opp_table(void)
{
	struct omap_opp_def *opp_def;
	struct device *dev;
	struct clk *gpu_fclk;
	int i, r;
        #if defined (CONFIG_MACH_LGE_CX2)
	struct omap_opp *tnt_opp;
	int has_tnt_opp = 0;
	#endif

	/*
	 * Allow multiple calls, but initialize only if not already initalized
	 * even if the previous call failed, coz, no reason we'd succeed again
	 */
	if (omap4_table_init)
		return 0;
	omap4_table_init = 1;

	if (omap_rev() <= OMAP4430_REV_ES2_0)
		opp_def = omap44xx_pre_es2_1_opp_def_list;
	else
		opp_def = omap44xx_opp_def_list;

	for (i = 0; i < omap44xx_opp_def_size; i++) {
		r = opp_add(opp_def);
		if (r)
			pr_err("unable to add OPP %ld Hz for %s\n",
				opp_def->freq, opp_def->hwmod_name);
		opp_def++;
	}

	dpll_mpu_clk = clk_get(NULL, "dpll_mpu_ck");
	iva_clk = clk_get(NULL, "dpll_iva_m5x2_ck");
	dsp_clk = clk_get(NULL, "dpll_iva_m4x2_ck");
	l3_clk = clk_get(NULL, "dpll_core_m5x2_ck");
	core_m2_clk = clk_get(NULL, "dpll_core_m2_ck");
	core_m3_clk = clk_get(NULL, "dpll_core_m3x2_ck");
	core_m6_clk = clk_get(NULL, "dpll_core_m6x2_ck");
	core_m7_clk = clk_get(NULL, "dpll_core_m7x2_ck");
	sgx_clk = clk_get(NULL, "dpll_per_m7x2_ck");
	gpu_fclk = clk_get(NULL, "gpu_fck");
	per_m3_clk = clk_get(NULL, "dpll_per_m3x2_ck");
	per_m6_clk = clk_get(NULL, "dpll_per_m6x2_ck");
	abe_clk = clk_get(NULL, "abe_clk");
	fdif_clk = clk_get(NULL, "fdif_fck");
	hsi_clk = clk_get(NULL, "hsi_fck");

	/* Set SGX parent to PER DPLL */
	clk_set_parent(gpu_fclk, sgx_clk);
	clk_put(gpu_fclk);

	/* Populate the set rate and get rate for mpu, iva, dsp and l3 device */
	dev = omap2_get_mpuss_device();
	if (dev)
		opp_populate_rate_fns(dev, omap4_mpu_set_rate,
				omap4_mpu_get_rate);

#if defined (CONFIG_MACH_LGE_CX2)
	/* Enable 1.2Gz OPP for silicon that supports it
	 * TODO: determine if FUSE_OPP_VDD_MPU_3 is a reliable source to
	 * determine 1.2Gz availability.
	 */
	has_tnt_opp = __raw_readl(OMAP2_L4_IO_ADDRESS(CTRL_FUSE_OPP_VDD_MPU_3));
	has_tnt_opp &= 0xFFFFFF;

	if (has_tnt_opp) {
		tnt_opp = opp_find_freq_exact(dev, TNT_FREQ, false);
		if (IS_ERR(tnt_opp))
		{
			printk(KERN_ERR"[1.2GHz support Fail] %d\n",tnt_opp);
			pr_err("unable to find OPP for 1.2Gz\n");
		}
		else
		{
			printk(KERN_ERR"[1.2GHz support success] %d\n",tnt_opp);
			opp_enable(tnt_opp);
		}
	}
#endif


	dev = omap2_get_iva_device();
	if (dev)
		opp_populate_rate_fns(dev, omap4_iva_set_rate,
				omap4_iva_get_rate);

	dev = omap4_get_dsp_device();
	if (dev)
		opp_populate_rate_fns(dev, omap4_iva_set_rate,
				omap4_iva_get_rate);

	dev = omap2_get_l3_device();
	if (dev)
		opp_populate_rate_fns(dev, omap4_l3_set_rate,
				omap4_l3_get_rate);

	/*
	 * This is a temporary hack since emif clocks cannot be scaled
	 * on ES1.0 and ES2.0. Once everybody has migrated to ES2.1 this
	 * check can be remove.
	 */
	if (omap_rev() > OMAP4430_REV_ES2_0) {
		dev = find_dev_ptr("emif1");
		if (dev)
			opp_populate_rate_fns(dev, omap4_emif_set_rate,
					omap4_emif_get_rate);

		dev = find_dev_ptr("emif2");
		if (dev)
			opp_populate_rate_fns(dev, omap4_emif_set_rate,
					omap4_emif_get_rate);
	}

	dev = find_dev_ptr("omap-aess-audio");
	if (dev)
		opp_populate_rate_fns(dev, omap4_abe_set_rate,
				omap4_abe_get_rate);

	dev = find_dev_ptr("gpu");
	if (dev)
		opp_populate_rate_fns(dev, omap4_sgx_set_rate,
				omap4_sgx_get_rate);

	dev = find_dev_ptr("fdif");
	if (dev)
		opp_populate_rate_fns(dev, omap4_fdif_set_rate,
				omap4_fdif_get_rate);

	dev = find_dev_ptr("hsi");
	if (dev)
		opp_populate_rate_fns(dev, omap4_hsi_set_rate,
				omap4_hsi_get_rate);

	return 0;
}