inline bool fiq_pending() const {return fiq_enable() && fiq_port.get();}
static __init void realview_irq_init(void)
{
u32_t i;
u32_t max_irq;
u32_t cpumask;
/* get cpumask */
cpumask = 1 << 0;
cpumask |= cpumask << 8;
cpumask |= cpumask << 16;
/* ignore all peripheral interrupt signals */
writel(REALVIEW_GIC1_DIST_CTRL, 0);
/*
* find out how many interrupts are supported.
* and the GIC only supports up to 1020 interrupt sources.
*/
max_irq = readl(REALVIEW_GIC1_DIST_CTR) & 0x1f;
max_irq = (max_irq + 1) * 32;
if(max_irq > 1020)
max_irq = 1020;
/*
* set all global interrupts to be level triggered, active low.
*/
for(i = 32; i < max_irq; i += 16)
writel(REALVIEW_GIC1_DIST_CONFIG + i * 4 / 16, 0);
/*
* set all global interrupts to this CPU only.
*/
for(i = 32; i < max_irq; i += 4)
writel(REALVIEW_GIC1_DIST_TARGET + i * 4 / 4, cpumask);
/*
* set priority on all interrupts.
*/
for(i = 0; i < max_irq; i += 4)
writel(REALVIEW_GIC1_DIST_PRI + i * 4 / 4, 0xa0a0a0a0);
/*
* disable all interrupts.
*/
for(i = 0; i < max_irq; i += 32)
writel(REALVIEW_GIC1_DIST_ENABLE_CLEAR + i * 4 / 32, 0xffffffff);
/* monitor the peripheral interrupt signals */
writel(REALVIEW_GIC1_DIST_CTRL, 1);
/* the priority mask level for cpu interface */
writel(REALVIEW_GIC1_CPU_PRIMASK, 0xf0);
/* enable signalling of interrupts */
writel(REALVIEW_GIC1_CPU_CTRL, 1);
/* initial irq's handler to null_irq_handler */
for(i = 0; i < ARRAY_SIZE(realview_irq_handler); i++)
{
realview_irq_handler[i] = (irq_handler)null_irq_handler;
}
for(i = 0; i < ARRAY_SIZE(realview_irqs); i++)
{
if(!irq_register(&realview_irqs[i]))
{
LOG_E("failed to register irq '%s'", realview_irqs[i].name);
}
}
/* enable irq and fiq */
irq_enable();
fiq_enable();
}
