void
fpga_set_rx_enable (unsigned char on)
{
on &= 0x1;
g_rx_enable = on;
write_fpga_master_ctrl ();
if (on){
g_rx_overrun = 0;
fpga_clear_flags ();
}
}
static void
main_loop (void)
{
setup_flowstate_common ();
while (1){
OEE = 0x0f;
IOE = 0x02; IOE = 0x01; // pulse two I/O pins
if (usb_setup_packet_avail ())
usb_handle_setup_packet ();
if (GPIFTRIG & bmGPIF_IDLE){
// OK, GPIF is idle. Let's try to give it some work.
// First check for underruns and overruns
#if 1
if (UC_BOARD_HAS_FPGA && (USRP_PA & (bmPA_TX_UNDERRUN | bmPA_RX_OVERRUN))){
// record the under/over run
if (USRP_PA & bmPA_TX_UNDERRUN)
g_tx_underrun = 1;
if (USRP_PA & bmPA_RX_OVERRUN)
g_rx_overrun = 1;
// tell the FPGA to clear the flags
fpga_clear_flags ();
}
#endif
// Next see if there are any "OUT" packets waiting for our attention,
// and if so, if there's room in the FPGA's FIFO for them.
if (g_tx_enable && !(EP24FIFOFLGS & 0x02)){ // USB end point fifo is not empty...
if (fpga_has_room_for_packet ()){ // ... and FPGA has room for packet
GPIFTCB1 = 0x01; SYNCDELAY;
GPIFTCB0 = 0x00; SYNCDELAY;
setup_flowstate_write ();
SYNCDELAY;
GPIFTRIG = bmGPIF_EP2_START | bmGPIF_WRITE; // start the xfer
SYNCDELAY;
while (!(GPIFTRIG & bmGPIF_IDLE)){
// wait for the transaction to complete
}
}
}
// See if there are any requests for "IN" packets, and if so
// whether the FPGA's got any packets for us.
if (g_rx_enable && !(EP6CS & bmEPFULL)){ // USB end point fifo is not full...
if (fpga_has_packet_avail ()){ // ... and FPGA has packet available
IOE = 0x08; // signal start of transfer
GPIFTCB1 = 0x01; SYNCDELAY;
GPIFTCB0 = 0x00; SYNCDELAY;
setup_flowstate_read ();
SYNCDELAY;
GPIFTRIG = bmGPIF_EP6_START | bmGPIF_READ; // start the xfer
SYNCDELAY;
while (!(GPIFTRIG & bmGPIF_IDLE)){
// wait for the transaction to complete
}
SYNCDELAY;
INPKTEND = 6; // tell USB we filled buffer (6 is our endpoint num)
IOE = 0x01; // signal end of transfer
}
}
}
}
}
