int main(int argc, char* argv[])
{
sys_stat stat;
int rtn;
fpga_reg_wr(0x400,0xA5A5A5A5);
rtn = fpga_reg_rd(0x400); //Read version register
printf("Register : %0x\n",rtn);
return 0;
}
/*Function to issue a soft reset to the user logic
Input : Reset active polarity
The function initially deasserts the reset, then asserts and again deasserts*/
void user_soft_reset(unsigned int polarity) {
int rtn;
rtn = fpga_reg_rd(UCTR_REG);
if(polarity == 0) {
fpga_reg_wr(UCTR_REG,rtn & 0xFFFFFFFF);
fpga_reg_wr(UCTR_REG,rtn & 0xFFFFFFFE);
fpga_reg_wr(UCTR_REG,rtn & 0xFFFFFFFF);
}
else {
fpga_reg_wr(UCTR_REG,rtn & 0xFFFFFFFE);
fpga_reg_wr(UCTR_REG,rtn & 0xFFFFFFFF);
fpga_reg_wr(UCTR_REG,rtn & 0xFFFFFFFE);
}
}
static long fpga_rw_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
{
int err = 0;
int retval = 0;
fpga_rw_reg_t fpga_rw_reg;
//printk("\n++++++++++++++enter ioctl fpga_rw_reg->pbuf = 0x%04x******************\n", fpga_rw_reg.addr);
if (_IOC_TYPE(cmd) != FPGA_RW_MAGIC)
return -ENOTTY;
if (_IOC_DIR(cmd) & _IOC_READ)
err = !access_ok(VERIFY_WRITE,
(void __user *)arg, _IOC_SIZE(cmd));
if (err == 0 && _IOC_DIR(cmd) & _IOC_WRITE)
err = !access_ok(VERIFY_READ,
(void __user *)arg, _IOC_SIZE(cmd));
if (err)
return -EFAULT;
if( copy_from_user(&fpga_rw_reg, (fpga_rw_reg_t *)arg, sizeof(fpga_rw_reg_t)) )
return -EFAULT;
mutex_lock(&ioctl_lock);
switch (cmd)
{
case FPGA_REG_RD:
//fpga_rw_reg.pbuf = fpga_vir_base[fpga_rw_reg.addr];
retval = fpga_reg_rd(&fpga_rw_reg);
if(retval == 0)
retval = copy_to_user((fpga_rw_reg_t *)arg, &fpga_rw_reg, sizeof(fpga_rw_reg_t) );
break;
case FPGA_REG_WR:
retval = fpga_reg_wt(&fpga_rw_reg);
break;
case FPGA_REG_RST:
retval = gpio_set_15(fpga_rw_reg.pbuf);
break;
default:
retval = -EINVAL;
break;
}
mutex_unlock(&ioctl_lock);
return retval;
}
int main()
{
float packet_time;
char buff[200] = "\0";
char wr_len[15];
int rtn,timeout,i,k;
int packet_num;
char pkt_num_str[15];
unsigned int arg = 100;
int rd_size = 1024*1;
int wr_size = 1024*1; // 64 KByte is the buffer-limit
int src_addr = 0x0;
int dst_addr = 1024;
int num_tx_pack = wr_size/1024;
timeout = 10*1000; // 10 secs.
FILE* ett = NULL;
ett = fopen("Res_eth_tx_test.txt","w+");
fclose(ett);
printf("Initializing DRAM at %0x with incremental pattern \n ",src_addr);
int test_val = 0x0;
for(i = 0; i < DATA_SIZE/4; i++){
senddata[i] = test_val;
test_val++;
}
rtn = fpga_send_data(DRAM, (unsigned char *) senddata,DATA_SIZE, src_addr);
// Loop Tests
for (k = 1; k <= 1024*1024; k=k*2) {
wr_size = 1024 * k;
// Eth SND DATA
printf("Setting Write size to %0x\n", wr_size);
rtn = fpga_reg_wr(ETH_TX_SIZE, wr_size);
printf("Setting DRAM source address to %0x\n",src_addr);
rtn = fpga_reg_wr(ETH_SRC_ADDR, src_addr);
rtn = fpga_reg_rd(0x40 );
printf("FPGA TX SIZE %0x \n",rtn);
printf("Enabling ethernet\n");
rtn = fpga_reg_wr( 0x8,0x00000004);
rtn = fpga_reg_rd( 0x10);
fpga_wait_interrupt(enet);
rtn = fpga_reg_rd(ETH_TX_STAT);
printf("FPGA ENET STS %0x \n",rtn);
packet_time = rtn * 5.0;
printf("Total Time : %0f ns\n",packet_time);
printf("Tpt : %0f MBps\n", (float)(wr_size/packet_time)*1000000000/1024/1024);
sprintf(wr_len,"%d",wr_size);
strcpy (buff,wr_len);
// strcat (buff," Bytes \n");
strcat (buff,",");
// strcat (buff,"Time : ");
// sprintf(wr_len,"%f",packet_time);
// strcat(buff,wr_len);
// strcat(buff,"\nTpt : ");
sprintf(wr_len,"%f", (float)(wr_size/packet_time)*1000000000/1024/1024);
strcat(buff,wr_len);
strcat(buff,"\n");
ett = fopen("Res_eth_tx_test.txt","a");
fwrite(&buff,1,strlen(buff),ett);
fclose(ett);
strcpy(buff,"\0");
//sleep(5);
}
printf("Exiting...");
}
