int main(int argc, char* argv[])
{
int rtn,i;
long usecs;
unsigned int test_size = 256;
printf("# data transfer between FPGA DRAM to user logic for different data size\n");
// printf("# Transfer Size(Bytes), Transfer Time (s),Throughput: (MB/s)\n");
//printf("Transfer Size(Bytes)\t\t\t\tThroughput: MB/s,\n");
//while(test_size <= DATA_SIZE) {
user_ddr_send_data(USERDRAM1,test_size,0x0,0);
user_ddr_send_data(USERDRAM2,test_size,0x0,0);
user_ddr_send_data(USERDRAM3,test_size,0x0,0);
user_ddr_send_data(USERDRAM4,test_size,0x0,0);
fpga_wait_interrupt(user1ddr);
fpga_wait_interrupt(user2ddr);
fpga_wait_interrupt(user3ddr);
fpga_wait_interrupt(user4ddr);
//printf("%d, %f, %f\n", test_size,(e-s)*1e-6,(double)(test_size*1000000.0)/(1024.0*1024.0*(double)(e-s)));
//printf("%d \t\t\t\t\t\t %f\n", 4*test_size,(double)(4*test_size*1000000.0)/(1024.0*1024.0*(double)(e-s)));
// test_size *= 2;
//}
return 0;
}
int main(int argc, char* argv[])
{
int rtn,i;
long usecs;
unsigned int arg = 0;
fpga_wait_interrupt(hostuser2);
}
/* Receiving data functions. */
int fpga_recv_data(DMA_PNT dest, unsigned char * recvdata, int recvlen, unsigned int addr) {
unsigned int rtn;
unsigned int len;
unsigned int size;
unsigned int amt;
unsigned int buf = 10;
unsigned int pre_buf = 11;
unsigned int tmp_buf;
unsigned int ddr_addr;
int copyd = 0;
int sent = 0;
int pre_amt = 0;
if(dest == USERPCIE1){
len = recvlen;
size = BUF_SIZE;
amt = len < size ? len : size;
rtn = write(fpgaDev->intrFds[buf], NULL, 0);
fpga_reg_wr(USER1_PC_DMA_SYS,rtn);
fpga_reg_wr(USER1_PC_DMA_LEN,amt);
fpga_reg_wr(CTRL_REG,RECV_USER1_DATA|0x00000001);
sent += amt;
pre_amt = amt;
while(1){
fpga_wait_interrupt(user1host); //Wait for interrupt from first buffer
if (sent < len) {
rtn = write(fpgaDev->intrFds[pre_buf], NULL, 0); //just to get the DMA buffer address
amt = (len-sent < size ? len-sent : size);
fpga_reg_wr(USER1_PC_DMA_SYS,rtn);
fpga_reg_wr(USER1_PC_DMA_LEN,amt);
fpga_reg_wr(CTRL_REG,RECV_USER1_DATA|0x00000001);
sent += amt;
}
rtn = read(fpgaDev->intrFds[buf],recvdata+copyd,pre_amt);
copyd += pre_amt;
if (copyd >= len) {
return copyd;
}
pre_amt = amt;
tmp_buf = buf;
buf = pre_buf;
pre_buf = tmp_buf;
}
}
else if(dest == USERPCIE2){
copyd = 0;
len = recvlen;
size = BUF_SIZE;
amt = len < size ? len : size;
rtn = write(fpgaDev->intrFds[buf], NULL, 0);
fpga_reg_wr(USER2_PC_DMA_SYS,rtn);
fpga_reg_wr(USER2_PC_DMA_LEN,amt);
fpga_reg_wr(CTRL_REG,RECV_USER2_DATA|0x00000001);
sent += amt;
pre_amt = amt;
while(1){
fpga_wait_interrupt(user2host); //Wait for interrupt from first buffer
if (sent < len) {
rtn = write(fpgaDev->intrFds[pre_buf], NULL, 0); //just to get the DMA buffer address
amt = (len-sent < size ? len-sent : size);
fpga_reg_wr(USER2_PC_DMA_SYS,rtn);
fpga_reg_wr(USER2_PC_DMA_LEN,amt);
fpga_reg_wr(CTRL_REG,RECV_USER2_DATA|0x00000001);
sent += amt;
}
rtn = read(fpgaDev->intrFds[buf],recvdata+copyd,pre_amt);
copyd += pre_amt;
if (copyd >= len) {
return copyd;
}
pre_amt = amt;
tmp_buf = buf;
buf = pre_buf;
pre_buf = tmp_buf;
}
}
else if(dest == USERPCIE3){
len = recvlen;
size = BUF_SIZE;
amt = len < size ? len : size;
rtn = write(fpgaDev->intrFds[buf], NULL, 0);
fpga_reg_wr(USER3_PC_DMA_SYS,rtn);
fpga_reg_wr(USER3_PC_DMA_LEN,amt);
fpga_reg_wr(CTRL_REG,RECV_USER3_DATA|0x00000001);
sent += amt;
pre_amt = amt;
while(1){
fpga_wait_interrupt(user3host); //Wait for interrupt from first buffer
if (sent < len) {
rtn = write(fpgaDev->intrFds[pre_buf], NULL, 0); //just to get the DMA buffer address
amt = (len-sent < size ? len-sent : size);
fpga_reg_wr(USER3_PC_DMA_SYS,rtn);
fpga_reg_wr(USER3_PC_DMA_LEN,amt);
fpga_reg_wr(CTRL_REG,RECV_USER3_DATA|0x00000001);
sent += amt;
}
rtn = read(fpgaDev->intrFds[buf],recvdata+copyd,pre_amt);
copyd += pre_amt;
if (copyd >= len) {
return copyd;
}
pre_amt = amt;
tmp_buf = buf;
buf = pre_buf;
pre_buf = tmp_buf;
}
}
else if(dest == USERPCIE4){
len = recvlen;
size = BUF_SIZE;
amt = len < size ? len : size;
rtn = write(fpgaDev->intrFds[buf], NULL, 0);
fpga_reg_wr(USER4_PC_DMA_SYS,rtn);
fpga_reg_wr(USER4_PC_DMA_LEN,amt);
fpga_reg_wr(CTRL_REG,RECV_USER4_DATA|0x00000001);
sent += amt;
pre_amt = amt;
while(1){
fpga_wait_interrupt(user4host); //Wait for interrupt from first buffer
if (sent < len) {
rtn = write(fpgaDev->intrFds[pre_buf], NULL, 0); //just to get the DMA buffer address
amt = (len-sent < size ? len-sent : size);
fpga_reg_wr(USER4_PC_DMA_SYS,rtn);
fpga_reg_wr(USER4_PC_DMA_LEN,amt);
fpga_reg_wr(CTRL_REG,RECV_USER4_DATA|0x00000001);
sent += amt;
}
rtn = read(fpgaDev->intrFds[buf],recvdata+copyd,pre_amt);
copyd += pre_amt;
if (copyd >= len) {
return copyd;
}
pre_amt = amt;
tmp_buf = buf;
buf = pre_buf;
pre_buf = tmp_buf;
}
}
else
printf("Wrong destination\n");
return 0;
}
/*The main function used to send PCIe data to the SWITCH DDR interface and the PCIe user stream interfaces
inputs : destination type (ddr, user1, user2 etc)
data buffer holdin the send data
total length of the transfer
target address in case of data transfer to DDR and blocking-non blocking indication in case of user data transfer
output : Returns total number of bytes sent
The function rounds the transfer size to 64byte boundary for PCIe packet requirement
The total transfer data is divided into 4MB chunks to fit into the host DMA buffers.
*/
int fpga_send_data(DMA_PNT dest, unsigned char * senddata, int sendlen, unsigned int addr) {
unsigned int rtn;
unsigned int len;
unsigned int ddr_addr;
unsigned int size = BUF_SIZE;
unsigned int amt;
unsigned int buf;
unsigned int pre_buf;
unsigned int tmp_buf;
int sent = 0;
if(dest == ICAP){
buf = 0;
pre_buf = 1;
ddr_addr = addr;
len = (sendlen+63)&0xFFFFFFC0; //Align length to 64 bytes
// Send initial transfer request.
amt = len < size ? len : size;
rtn = write(fpgaDev->intrFds[0], senddata, amt);
fpga_reg_wr(0x50,rtn);
// fpga_reg_wr(PC_DDR_DMA_FPGA_REG,ddr_addr);
fpga_reg_wr(0x54,amt);
fpga_reg_wr(CTRL_REG,0x100001);
ddr_addr += amt;
sent += amt;
// Still more data, send to next buffer
if (sent < len) {
amt = (len-sent < size ? len-sent : size);
rtn = write(fpgaDev->intrFds[1], senddata+sent, amt);
}
while(1){
fpga_wait_interrupt(config); //Wait for interrupt from first buffer
if (sent < len) {
fpga_reg_wr(0x50,rtn);
// fpga_reg_wr(PC_DDR_DMA_FPGA_REG,ddr_addr);
fpga_reg_wr(0x54,amt);
fpga_reg_wr(CTRL_REG,0x100001);
ddr_addr += amt;
sent += amt;
tmp_buf = buf;
buf = pre_buf;
pre_buf = tmp_buf;
if (sent < len) {
amt = (len-sent < size ? len-sent : size);
rtn = write(fpgaDev->intrFds[pre_buf], senddata+sent, amt);
}
}
else{
return sent;
}
}
}
else if(dest == USERPCIE1){
buf = 0;
pre_buf = 1;
len = sendlen;
amt = len < size ? len : size;
rtn = write(fpgaDev->intrFds[0], senddata, amt);
fpga_reg_wr(PC_USER1_DMA_SYS,rtn);
fpga_reg_wr(PC_USER1_DMA_LEN,amt);
fpga_reg_wr(CTRL_REG,SEND_USER1_DATA|0x00000001);
//printf("Buffer address is %0x\n",rtn);
sent += amt;
// Still more data, send to next buffer
if (sent < len) {
amt = (len-sent < size ? len-sent : size);
rtn = write(fpgaDev->intrFds[1], senddata+sent, amt);
}
if(addr != 0){
while(1){
fpga_wait_interrupt(hostuser1);
if (sent < len) {
fpga_reg_wr(PC_USER1_DMA_SYS,rtn);
fpga_reg_wr(PC_USER1_DMA_LEN,amt);
fpga_reg_wr(CTRL_REG,SEND_USER1_DATA|0x00000001);
//printf("Buffer address is %0x\n",rtn);
sent += amt;
sent += amt;
tmp_buf = buf;
buf = pre_buf;
pre_buf = tmp_buf;
if (sent < len){
amt = (len-sent < size ? len-sent : size);
rtn = write(fpgaDev->intrFds[pre_buf], senddata+sent, amt);
}
}
else
return sent;
}
}
}
else if(dest == USERPCIE2){
buf = 2;
pre_buf = 3;
len = sendlen;
amt = len < size ? len : size;
rtn = write(fpgaDev->intrFds[2], senddata, amt);
fpga_reg_wr(PC_USER2_DMA_SYS,rtn);
fpga_reg_wr(PC_USER2_DMA_LEN,amt);
fpga_reg_wr(CTRL_REG,SEND_USER2_DATA|0x00000001);
//printf("Buffer address is %0x\n",rtn);
sent += amt;
sent += amt;
// Still more data, send to next buffer
if (sent < len) {
amt = (len-sent < size ? len-sent : size);
rtn = write(fpgaDev->intrFds[3], senddata+sent, amt);
}
if(addr != 0){
while(1){
fpga_wait_interrupt(hostuser2);
if (sent < len) {
fpga_reg_wr(PC_USER2_DMA_SYS,rtn);
fpga_reg_wr(PC_USER2_DMA_LEN,amt);
fpga_reg_wr(CTRL_REG,SEND_USER2_DATA|0x00000001);
//printf("Buffer address is %0x\n",rtn);
sent += amt;
sent += amt;
tmp_buf = buf;
buf = pre_buf;
pre_buf = tmp_buf;
if (sent < len){
amt = (len-sent < size ? len-sent : size);
rtn = write(fpgaDev->intrFds[pre_buf], senddata+sent, amt);
}
}
else
return sent;
}
}
}
else if(dest == USERPCIE3){
buf = 4;
pre_buf = 5;
len = sendlen;
amt = len < size ? len : size;
rtn = write(fpgaDev->intrFds[4], senddata, amt);
fpga_reg_wr(PC_USER3_DMA_SYS,rtn);
fpga_reg_wr(PC_USER3_DMA_LEN,amt);
fpga_reg_wr(CTRL_REG,SEND_USER3_DATA|0x00000001);
//printf("Buffer address is %0x\n",rtn);
sent += amt;
sent += amt;
// Still more data, send to next buffer
if (sent < len) {
amt = (len-sent < size ? len-sent : size);
rtn = write(fpgaDev->intrFds[5], senddata+sent, amt);
}
if(addr != 0){
while(1){
fpga_wait_interrupt(hostuser3);
if (sent < len) {
fpga_reg_wr(PC_USER3_DMA_SYS,rtn);
fpga_reg_wr(PC_USER3_DMA_LEN,amt);
fpga_reg_wr(CTRL_REG,SEND_USER3_DATA|0x00000001);
//printf("Buffer address is %0x\n",rtn);
sent += amt;
sent += amt;
tmp_buf = buf;
buf = pre_buf;
pre_buf = tmp_buf;
if (sent < len){
amt = (len-sent < size ? len-sent : size);
rtn = write(fpgaDev->intrFds[pre_buf], senddata+sent, amt);
}
}
else
return sent;
}
}
}
else if(dest == USERPCIE4){
buf = 6;
pre_buf = 7;
len = sendlen;
amt = len < size ? len : size;
rtn = write(fpgaDev->intrFds[6], senddata, amt);
fpga_reg_wr(PC_USER4_DMA_SYS,rtn);
fpga_reg_wr(PC_USER4_DMA_LEN,amt);
fpga_reg_wr(CTRL_REG,SEND_USER4_DATA|0x00000001);
//printf("Buffer address is %0x\n",rtn);
sent += amt;
sent += amt;
// Still more data, send to next buffer
if (sent < len) {
amt = (len-sent < size ? len-sent : size);
rtn = write(fpgaDev->intrFds[7], senddata+sent, amt);
}
if(addr != 0){
while(1){
fpga_wait_interrupt(hostuser4);
if (sent < len) {
fpga_reg_wr(PC_USER4_DMA_SYS,rtn);
fpga_reg_wr(PC_USER4_DMA_LEN,amt);
fpga_reg_wr(CTRL_REG,SEND_USER4_DATA|0x00000001);
//printf("Buffer address is %0x\n",rtn);
sent += amt;
sent += amt;
tmp_buf = buf;
buf = pre_buf;
pre_buf = tmp_buf;
if (sent < len){
amt = (len-sent < size ? len-sent : size);
rtn = write(fpgaDev->intrFds[pre_buf], senddata+sent, amt);
}
}
else
return sent;
}
}
}
else
printf("Wrong destination\n");
return 0;
}
int main()
{
float packet_time;
char buff[200] = "\0";
char wr_len[15];
int rtn,timeout,i,k;
int packet_num;
char pkt_num_str[15];
unsigned int arg = 100;
int rd_size = 1024*1;
int wr_size = 1024*1; // 64 KByte is the buffer-limit
int src_addr = 0x0;
int dst_addr = 1024;
int num_tx_pack = wr_size/1024;
timeout = 10*1000; // 10 secs.
FILE* ett = NULL;
ett = fopen("Res_eth_tx_test.txt","w+");
fclose(ett);
printf("Initializing DRAM at %0x with incremental pattern \n ",src_addr);
int test_val = 0x0;
for(i = 0; i < DATA_SIZE/4; i++){
senddata[i] = test_val;
test_val++;
}
rtn = fpga_send_data(DRAM, (unsigned char *) senddata,DATA_SIZE, src_addr);
// Loop Tests
for (k = 1; k <= 1024*1024; k=k*2) {
wr_size = 1024 * k;
// Eth SND DATA
printf("Setting Write size to %0x\n", wr_size);
rtn = fpga_reg_wr(ETH_TX_SIZE, wr_size);
printf("Setting DRAM source address to %0x\n",src_addr);
rtn = fpga_reg_wr(ETH_SRC_ADDR, src_addr);
rtn = fpga_reg_rd(0x40 );
printf("FPGA TX SIZE %0x \n",rtn);
printf("Enabling ethernet\n");
rtn = fpga_reg_wr( 0x8,0x00000004);
rtn = fpga_reg_rd( 0x10);
fpga_wait_interrupt(enet);
rtn = fpga_reg_rd(ETH_TX_STAT);
printf("FPGA ENET STS %0x \n",rtn);
packet_time = rtn * 5.0;
printf("Total Time : %0f ns\n",packet_time);
printf("Tpt : %0f MBps\n", (float)(wr_size/packet_time)*1000000000/1024/1024);
sprintf(wr_len,"%d",wr_size);
strcpy (buff,wr_len);
// strcat (buff," Bytes \n");
strcat (buff,",");
// strcat (buff,"Time : ");
// sprintf(wr_len,"%f",packet_time);
// strcat(buff,wr_len);
// strcat(buff,"\nTpt : ");
sprintf(wr_len,"%f", (float)(wr_size/packet_time)*1000000000/1024/1024);
strcat(buff,wr_len);
strcat(buff,"\n");
ett = fopen("Res_eth_tx_test.txt","a");
fwrite(&buff,1,strlen(buff),ett);
fclose(ett);
strcpy(buff,"\0");
//sleep(5);
}
printf("Exiting...");
}
