static int syscall_write_mem (host_callback *cb, struct cb_syscall *sc, unsigned long taddr, const char *buf, int bytes) { SIM_DESC sd = (SIM_DESC) sc->p1; SIM_CPU *cpu = (SIM_CPU *) sc->p2; frv_cache_invalidate_all (CPU_INSN_CACHE (cpu), 0); frv_cache_invalidate_all (CPU_DATA_CACHE (cpu), 1); return sim_core_write_buffer (sd, cpu, write_map, buf, taddr, bytes); }
/* Perform a hardware reset. */ void frv_hardware_reset (SIM_CPU *cpu) { /* GR, FR and CPR registers are undefined at hardware reset. */ frv_initialize_spr (cpu); /* Reset the RSTR register (in memory). */ if (frv_cache_enabled (CPU_DATA_CACHE (cpu))) frvbf_mem_set_SI (cpu, CPU_PC_GET (cpu), RSTR_ADDRESS, RSTR_HARDWARE_RESET); else SETMEMSI (cpu, CPU_PC_GET (cpu), RSTR_ADDRESS, RSTR_HARDWARE_RESET); /* Reset the insn and data caches. */ frv_cache_invalidate_all (CPU_INSN_CACHE (cpu), 0/* no flush */); frv_cache_invalidate_all (CPU_DATA_CACHE (cpu), 0/* no flush */); }
void frv_sim_engine_halt_hook (SIM_DESC sd, SIM_CPU *current_cpu, sim_cia cia) { int i; if (current_cpu != NULL) CIA_SET (current_cpu, cia); /* Invalidate the insn and data caches of all cpus. */ for (i = 0; i < MAX_NR_PROCESSORS; ++i) { current_cpu = STATE_CPU (sd, i); frv_cache_invalidate_all (CPU_INSN_CACHE (current_cpu), 0); frv_cache_invalidate_all (CPU_DATA_CACHE (current_cpu), 1); } frv_term (sd); }
static void handle_req_invalidate (FRV_CACHE *cache, int pipe, FRV_CACHE_REQUEST *req) { FRV_CACHE_PIPELINE *pipeline = & cache->pipeline[pipe]; SI address = req->address; SI interfere_address = req->u.invalidate.all ? -1 : address; /* If this address interferes with an existing request, then requeue it. */ if (address_interference (cache, interfere_address, req, pipe)) { pipeline_requeue_request (pipeline); return; } /* Invalidate the cache line now. This function already checks for non-cache access. */ if (req->u.invalidate.all) frv_cache_invalidate_all (cache, req->u.invalidate.flush); else frv_cache_invalidate (cache, address, req->u.invalidate.flush); if (req->u.invalidate.flush) { pipeline->status.flush.reqno = req->reqno; pipeline->status.flush.address = address; pipeline->status.flush.valid = 1; } }