/****************************************************************************
Apply desired action depending on user's request (clicked button).
****************************************************************************/
void option_dialog::apply_option(int response)
{
switch (response) {
case RESPONSE_APPLY:
apply_options();
break;
case RESPONSE_CANCEL:
::dialog_list.remove(curr_options);
close();
break;
case RESPONSE_OK:
apply_options();
::dialog_list.remove(curr_options);
close();
break;
case RESPONSE_SAVE:
desired_settable_options_update();
options_save();
break;
case RESPONSE_RESET:
full_reset();
break;
case RESPONSE_REFRESH:
full_refresh();
break;
}
}
static void do_fsp_post_memory_init(bool s3wake, uint32_t fsp_version)
{
struct range_entry fsp_mem;
if (fsp_find_reserved_memory(&fsp_mem))
die("Failed to find FSP_RESERVED_MEMORY_RESOURCE_HOB!\n");
/* initialize cbmem by adding FSP reserved memory first thing */
if (!s3wake) {
cbmem_initialize_empty_id_size(CBMEM_ID_FSP_RESERVED_MEMORY,
range_entry_size(&fsp_mem));
} else if (cbmem_initialize_id_size(CBMEM_ID_FSP_RESERVED_MEMORY,
range_entry_size(&fsp_mem))) {
if (CONFIG(HAVE_ACPI_RESUME)) {
printk(BIOS_ERR,
"Failed to recover CBMEM in S3 resume.\n");
/* Failed S3 resume, reset to come up cleanly */
/* FIXME: A "system" reset is likely enough: */
full_reset();
}
}
/* make sure FSP memory is reserved in cbmem */
if (range_entry_base(&fsp_mem) !=
(uintptr_t)cbmem_find(CBMEM_ID_FSP_RESERVED_MEMORY))
die("Failed to accommodate FSP reserved memory request!\n");
save_memory_training_data(s3wake, fsp_version);
/* Create romstage handof information */
romstage_handoff_init(s3wake);
}
static enum cb_err fsp_fill_common_arch_params(FSPM_ARCH_UPD *arch_upd,
bool s3wake, uint32_t fsp_version,
const struct memranges *memmap)
{
if (setup_fsp_stack_frame(arch_upd, memmap))
return CB_ERR;
fsp_fill_mrc_cache(arch_upd, fsp_version);
/* Configure bootmode */
if (s3wake) {
/*
* For S3 resume case, if valid mrc cache data is not found or
* RECOVERY_MRC_CACHE hash verification fails, the S3 data
* pointer would be null and S3 resume fails with fsp-m
* returning error. Invoking a reset here saves time.
*/
if (!arch_upd->NvsBufferPtr)
/* FIXME: A "system" reset is likely enough: */
full_reset();
arch_upd->BootMode = FSP_BOOT_ON_S3_RESUME;
} else {
if (arch_upd->NvsBufferPtr)
arch_upd->BootMode =
FSP_BOOT_ASSUMING_NO_CONFIGURATION_CHANGES;
else
arch_upd->BootMode = FSP_BOOT_WITH_FULL_CONFIGURATION;
}
printk(BIOS_SPEW, "bootmode is set to :%d\n", arch_upd->BootMode);
return CB_SUCCESS;
}
static void power_down_reset_check(void)
{
uint8_t cmos;
cmos=cmos_read(RTC_BOOT_BYTE)>>4 ;
print_debug("Boot byte = ");
print_debug_hex8(cmos);
print_debug("\n");
if((cmos>2)&&(cmos&1)) full_reset();
}
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
printf("Resetting the board...");
milisecdelay(500);
full_reset();
/* After full chip reset we should not reach next step... */
printf("\n## Error: RESET FAILED!\n");
return 0;
}
static void check_full_retrain(const FSPM_UPD *mupd)
{
struct chipset_power_state *ps;
if (mupd->FspmArchUpd.BootMode != FSP_BOOT_WITH_FULL_CONFIGURATION)
return;
ps = pmc_get_power_state();
if (ps->gen_pmcon1 & WARM_RESET_STS) {
printk(BIOS_INFO, "Full retrain unsupported on warm reboot.\n");
full_reset();
}
}
static void mainboard_set_e7520_pll(unsigned bits)
{
uint16_t gpio_index;
uint8_t data;
device_t dev;
/* currently only handle the Jarrell/PC87427 case */
dev = PC87427_GPIO_DEV;
pnp_set_logical_device(dev);
gpio_index = pnp_read_iobase(dev, 0x60);
/* select SIO GPIO port 4, pin 2 */
pnp_write_config(dev, PC87427_GPSEL, ((pnp_read_config(dev, PC87427_GPSEL) & 0x88) | 0x42));
/* set to push-pull, enable output */
pnp_write_config(dev, PC87427_GPCFG1, 0x03);
/* select SIO GPIO port 4, pin 4 */
pnp_write_config(dev, PC87427_GPSEL, ((pnp_read_config(dev, PC87427_GPSEL) & 0x88) | 0x44));
/* set to push-pull, enable output */
pnp_write_config(dev, PC87427_GPCFG1, 0x03);
/* set gpio 42,44 signal levels */
data = inb(gpio_index + PC87427_GPDO_4);
if ((data & 0x14) == (0xff & (((bits&2)?0:1)<<4 | ((bits&1)?0:1)<<2))) {
print_debug("set_pllsel: correct settings detected!\n");
return; /* settings already configured */
} else {
outb((data & 0xeb) | ((bits&2)?0:1)<<4 | ((bits&1)?0:1)<<2, gpio_index + PC87427_GPDO_4);
/* reset */
print_debug("set_pllsel: settings adjusted, now resetting...\n");
// hard_reset(); /* should activate a PCI_RST, which should reset MCH, but it doesn't seem to work ???? */
// mch_reset();
full_reset();
}
return;
}
