static int bcm_init(struct uec_mii_info *mii_info) { struct eth_device *edev = mii_info->dev; uec_private_t *uec = edev->priv; gbit_config_aneg(mii_info); if ((uec->uec_info->enet_interface_type == PHY_INTERFACE_MODE_RGMII_RXID) && (uec->uec_info->speed == SPEED_1000)) { u16 val; int cnt = 50; /* Wait for aneg to complete. */ do val = uec_phy_read(mii_info, MII_BMSR); while (--cnt && !(val & BMSR_ANEGCOMPLETE)); /* Set RDX clk delay. */ uec_phy_write(mii_info, 0x18, 0x7 | (7 << 12)); val = uec_phy_read(mii_info, 0x18); /* Set RDX-RXC skew. */ val |= (1 << 8); val |= (7 | (7 << 12)); /* Write bits 14:0. */ val |= (1 << 15); uec_phy_write(mii_info, 0x18, val); } return 0; }
static int marvell_config_aneg(struct gfar_mii_info *mii_info) { /* The Marvell PHY has an errata which requires * that certain registers get written in order * to restart autonegotiation */ phy_write(mii_info, MII_BMCR, BMCR_RESET); phy_write(mii_info, 0x1d, 0x1f); phy_write(mii_info, 0x1e, 0x200c); phy_write(mii_info, 0x1d, 0x5); phy_write(mii_info, 0x1e, 0); phy_write(mii_info, 0x1e, 0x100); gbit_config_aneg(mii_info); return 0; }
static int marvell_config_aneg(struct ugeth_mii_info *mii_info) { ugphy_vdbg("%s: IN", __FUNCTION__); /* The Marvell PHY has an errata which requires * that certain registers get written in order * to restart autonegotiation */ ucc_geth_phy_write(mii_info, MII_BMCR, BMCR_RESET); ucc_geth_phy_write(mii_info, 0x1d, 0x1f); ucc_geth_phy_write(mii_info, 0x1e, 0x200c); ucc_geth_phy_write(mii_info, 0x1d, 0x5); ucc_geth_phy_write(mii_info, 0x1e, 0); ucc_geth_phy_write(mii_info, 0x1e, 0x100); gbit_config_aneg(mii_info); return 0; }