int gen10g_config(struct phy_device *phydev)
{
/* For now, assume 10000baseT. Fill in later */
phydev->supported = phydev->advertising = SUPPORTED_10000baseT_Full;
return gen10g_discover_mmds(phydev);
}
/**
* Resets the PHY on the NIC10e 66
*
* Revision 2 of the NIC10e board requires a special reset sequence for
* the Broadcom BCM8727 PHY device if the SPI-ROM is installed. A normal
* reset sequence will prevent the PHY device from working properly.
*
* Revision 1 of the NIC10e board does not have the SPI-ROM and revision 3
* uses a Vitesse device. Both the revision 1 and revision 3 boards can
* use the standard PHY reset code.
*
* @param phydev - pointer to phy device data structure
*
* @return 0 for success, -1 on error.
*/
static int nic10e_phy_reset(struct phy_device *phydev)
{
int reg;
int timeout = 500;
int devad = MDIO_DEVAD_NONE;
debug("In %s\n", __func__);
/* If it's 10G, we need to issue reset through one of the MMDs */
if (!is_10g_interface(phydev->interface)) {
printf("%s: Error: phy not 10G interface\n", __func__);
return -1;
}
if (!phydev->mmds)
gen10g_discover_mmds(phydev);
devad = ffs(phydev->mmds);
reg = phy_read(phydev, devad, MII_BMCR);
if (reg < 0) {
debug("PHY status read failed\n");
return -1;
}
/* The below sequence comes from the BCM8727 data sheet when the
* PMD Adaptive Equalizer is to be configured.
*
*/
reg |= BMCR_RESET;
/* The BCM8727 PHY does not recover after a reset command if the SPI-ROM
* is installed.
*/
if (gd->arch.board_desc.rev_major == 2) {
debug("Not resetting PHY due to PHY brokeness\n");
return 0;
/* For the BCM8727 with the SPI-ROM turn on the SPI interface */
if (phy_write(phydev, devad, BCM8727_MISC_CTRL2, 1) < 0)
return -1;
}
debug("Resetting phy at %d %d\n", phydev->addr, devad);
/* Issue soft reset */
if (phy_write(phydev, devad, MII_BMCR, reg) < 0)
return -1;
if (gd->arch.board_desc.rev_major == 2) {
/* General control status register global reset */
if (phy_write(phydev, devad, BCM8727_GEN_CTRL_STAT, 1) < 0)
return -1;
/* 78 MHz uC clock
* Force 8051 SPI port reboot at next reset,
* Soft reset the microcontroller
*/
if (phy_write(phydev, devad, BCM8727_GEN_CTRL_STAT, 0x18c) < 0)
return -1;
/* Enable microcode upload from external SPI-ROM */
if (phy_write(phydev, devad, BCM8727_MISC_CTRL2, 1) < 0)
return -1;
/* refclk derived from REFCLK input
* 78MHz
* Force an 8051 SPI port reboot at next reset
* Soft reset of internal logic (register values retained)
*/
if (phy_write(phydev, devad, BCM8727_GEN_CTRL_STAT, 0x018a) < 0)
return -1;
/* Take internal logic out of reset */
if (phy_write(phydev, devad, BCM8727_GEN_CTRL_STAT, 0x0188) < 0)
return -1;
/* Give time to load firmware, spec says 100ms */
mdelay(100);
/* Disable serial boot and put SPI eeprom in tri-state mode */
if (phy_write(phydev, devad, BCM8727_MISC_CTRL2, 0) < 0)
return -1;
}
/*
* Poll the control register for the reset bit to go to 0 (it is
* auto-clearing). This should happen within 0.5 seconds per the
* IEEE spec.
*/
while ((reg & BMCR_RESET) && timeout--) {
reg = phy_read(phydev, devad, MII_BMCR);
if (reg < 0) {
debug("PHY status read failed\n");
return -1;
}
mdelay(1);
}
if (reg & BMCR_RESET) {
puts("PHY reset timed out\n");
return -1;
}
return 0;
}
