/**
* \copydoc gen6_blorp_exec()
*/
void
gen7_blorp_exec(struct brw_context *brw,
const struct brw_blorp_params *params)
{
if (brw->gen >= 8)
return;
uint32_t cc_blend_state_offset = 0;
uint32_t cc_state_offset = 0;
uint32_t depthstencil_offset;
uint32_t wm_push_const_offset = 0;
uint32_t wm_bind_bo_offset = 0;
brw_upload_state_base_address(brw);
gen6_emit_3dstate_multisample(brw, params->dst.num_samples);
gen6_emit_3dstate_sample_mask(brw,
params->dst.num_samples > 1 ?
(1 << params->dst.num_samples) - 1 : 1);
gen6_blorp_emit_vertices(brw, params);
gen7_blorp_emit_urb_config(brw);
if (params->wm_prog_data) {
cc_blend_state_offset = gen6_blorp_emit_blend_state(brw, params);
cc_state_offset = gen6_blorp_emit_cc_state(brw);
gen7_blorp_emit_blend_state_pointer(brw, cc_blend_state_offset);
gen7_blorp_emit_cc_state_pointer(brw, cc_state_offset);
}
depthstencil_offset = gen6_blorp_emit_depth_stencil_state(brw, params);
gen7_blorp_emit_depth_stencil_state_pointers(brw, depthstencil_offset);
if (brw->use_resource_streamer)
gen7_disable_hw_binding_tables(brw);
if (params->wm_prog_data) {
uint32_t wm_surf_offset_renderbuffer;
uint32_t wm_surf_offset_texture = 0;
wm_push_const_offset = gen6_blorp_emit_wm_constants(brw, params);
intel_miptree_used_for_rendering(params->dst.mt);
wm_surf_offset_renderbuffer =
gen7_blorp_emit_surface_state(brw, ¶ms->dst,
I915_GEM_DOMAIN_RENDER,
I915_GEM_DOMAIN_RENDER,
true /* is_render_target */);
if (params->src.mt) {
wm_surf_offset_texture =
gen7_blorp_emit_surface_state(brw, ¶ms->src,
I915_GEM_DOMAIN_SAMPLER, 0,
false /* is_render_target */);
}
wm_bind_bo_offset =
gen6_blorp_emit_binding_table(brw,
wm_surf_offset_renderbuffer,
wm_surf_offset_texture);
}
gen7_blorp_emit_vs_disable(brw);
gen7_blorp_emit_hs_disable(brw);
gen7_blorp_emit_te_disable(brw);
gen7_blorp_emit_ds_disable(brw);
gen7_blorp_emit_gs_disable(brw);
gen7_blorp_emit_streamout_disable(brw);
gen6_blorp_emit_clip_disable(brw);
gen7_blorp_emit_sf_config(brw, params);
gen7_blorp_emit_wm_config(brw, params);
if (params->wm_prog_data) {
gen7_blorp_emit_binding_table_pointers_ps(brw, wm_bind_bo_offset);
gen7_blorp_emit_constant_ps(brw, wm_push_const_offset);
} else {
gen7_blorp_emit_constant_ps_disable(brw);
}
if (params->src.mt) {
const uint32_t sampler_offset =
gen6_blorp_emit_sampler_state(brw, BRW_MAPFILTER_LINEAR, 0, true);
gen7_blorp_emit_sampler_state_pointers_ps(brw, sampler_offset);
}
gen7_blorp_emit_ps_config(brw, params);
gen7_blorp_emit_cc_viewport(brw);
if (params->depth.mt)
gen7_blorp_emit_depth_stencil_config(brw, params);
else
gen7_blorp_emit_depth_disable(brw);
gen7_blorp_emit_clear_params(brw, params);
gen6_blorp_emit_drawing_rectangle(brw, params);
gen7_blorp_emit_primitive(brw, params);
}
void
brw_emit_select_pipeline(struct brw_context *brw, enum brw_pipeline pipeline)
{
const bool is_965 = brw->gen == 4 && !brw->is_g4x;
const uint32_t _3DSTATE_PIPELINE_SELECT =
is_965 ? CMD_PIPELINE_SELECT_965 : CMD_PIPELINE_SELECT_GM45;
if (brw->use_resource_streamer && pipeline != BRW_RENDER_PIPELINE) {
/* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
* PIPELINE_SELECT [DevBWR+]":
*
* Project: HSW, BDW, CHV, SKL, BXT
*
* Hardware Binding Tables are only supported for 3D
* workloads. Resource streamer must be enabled only for 3D
* workloads. Resource streamer must be disabled for Media and GPGPU
* workloads.
*/
BEGIN_BATCH(1);
OUT_BATCH(MI_RS_CONTROL | 0);
ADVANCE_BATCH();
gen7_disable_hw_binding_tables(brw);
/* XXX - Disable gather constant pool too when we start using it. */
}
if (brw->gen >= 8 && brw->gen < 10) {
/* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:
*
* Software must clear the COLOR_CALC_STATE Valid field in
* 3DSTATE_CC_STATE_POINTERS command prior to send a PIPELINE_SELECT
* with Pipeline Select set to GPGPU.
*
* The internal hardware docs recommend the same workaround for Gen9
* hardware too.
*/
if (pipeline == BRW_COMPUTE_PIPELINE) {
BEGIN_BATCH(2);
OUT_BATCH(_3DSTATE_CC_STATE_POINTERS << 16 | (2 - 2));
OUT_BATCH(0);
ADVANCE_BATCH();
brw->ctx.NewDriverState |= BRW_NEW_CC_STATE;
}
} else if (brw->gen >= 6) {
/* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
* PIPELINE_SELECT [DevBWR+]":
*
* Project: DEVSNB+
*
* Software must ensure all the write caches are flushed through a
* stalling PIPE_CONTROL command followed by another PIPE_CONTROL
* command to invalidate read only caches prior to programming
* MI_PIPELINE_SELECT command to change the Pipeline Select Mode.
*/
const unsigned dc_flush =
brw->gen >= 7 ? PIPE_CONTROL_DATA_CACHE_FLUSH : 0;
if (brw->gen == 6) {
/* Hardware workaround: SNB B-Spec says:
*
* Before a PIPE_CONTROL with Write Cache Flush Enable = 1, a
* PIPE_CONTROL with any non-zero post-sync-op is required.
*/
brw_emit_post_sync_nonzero_flush(brw);
}
brw_emit_pipe_control_flush(brw,
PIPE_CONTROL_RENDER_TARGET_FLUSH |
PIPE_CONTROL_DEPTH_CACHE_FLUSH |
dc_flush |
PIPE_CONTROL_NO_WRITE |
PIPE_CONTROL_CS_STALL);
brw_emit_pipe_control_flush(brw,
PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
PIPE_CONTROL_CONST_CACHE_INVALIDATE |
PIPE_CONTROL_STATE_CACHE_INVALIDATE |
PIPE_CONTROL_INSTRUCTION_INVALIDATE |
PIPE_CONTROL_NO_WRITE);
} else {
/* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
* PIPELINE_SELECT [DevBWR+]":
*
* Project: PRE-DEVSNB
*
* Software must ensure the current pipeline is flushed via an
* MI_FLUSH or PIPE_CONTROL prior to the execution of PIPELINE_SELECT.
*/
BEGIN_BATCH(1);
OUT_BATCH(MI_FLUSH);
ADVANCE_BATCH();
}
/* Select the pipeline */
BEGIN_BATCH(1);
OUT_BATCH(_3DSTATE_PIPELINE_SELECT << 16 |
(brw->gen >= 9 ? (3 << 8) : 0) |
(pipeline == BRW_COMPUTE_PIPELINE ? 2 : 0));
ADVANCE_BATCH();
if (brw->gen == 7 && !brw->is_haswell &&
pipeline == BRW_RENDER_PIPELINE) {
/* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
* PIPELINE_SELECT [DevBWR+]":
*
* Project: DEVIVB, DEVHSW:GT3:A0
*
* Software must send a pipe_control with a CS stall and a post sync
* operation and then a dummy DRAW after every MI_SET_CONTEXT and
* after any PIPELINE_SELECT that is enabling 3D mode.
*/
gen7_emit_cs_stall_flush(brw);
BEGIN_BATCH(7);
OUT_BATCH(CMD_3D_PRIM << 16 | (7 - 2));
OUT_BATCH(_3DPRIM_POINTLIST);
OUT_BATCH(0);
OUT_BATCH(0);
OUT_BATCH(0);
OUT_BATCH(0);
OUT_BATCH(0);
ADVANCE_BATCH();
}
if (brw->use_resource_streamer && pipeline == BRW_RENDER_PIPELINE) {
/* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
* PIPELINE_SELECT [DevBWR+]":
*
* Project: HSW, BDW, CHV, SKL, BXT
*
* Hardware Binding Tables are only supported for 3D
* workloads. Resource streamer must be enabled only for 3D
* workloads. Resource streamer must be disabled for Media and GPGPU
* workloads.
*/
BEGIN_BATCH(1);
OUT_BATCH(MI_RS_CONTROL | 1);
ADVANCE_BATCH();
gen7_enable_hw_binding_tables(brw);
/* XXX - Re-enable gather constant pool here. */
}
}
