示例#1
0
/*
 * Example:
 * setenv videomode video=ctfb:x:800,y:480,depth:16,mode:0,\
 *            pclk:30066,le:41,ri:89,up:45,lo:12,
 *            hs:1,vs:1,sync:100663296,vmode:0
 */
static void s3c_lcd_init(GraphicDevice *panel,
			struct ctfb_res_modes *mode, int bpp)
{
	uint32_t clk_divider;
	struct s3c24x0_lcd *regs = s3c24x0_get_base_lcd();

	/* Stop the controller. */
	clrbits_le32(&regs->lcdcon1, 1);

	/* Calculate clock divider. */
	clk_divider = (get_HCLK() / PS2KHZ(mode->pixclock)) / 1000;
	clk_divider = DIV_ROUND_UP(clk_divider, 2);
	if (clk_divider)
		clk_divider -= 1;

	/* Program LCD configuration. */
	switch (bpp) {
	case 16:
		writel(S3CFB_LCDCON1_BPPMODE_TFT_16BPP |
		       S3CFB_LCDCON1_PNRMODE_TFT |
		       S3CFB_LCDCON1_CLKVAL(clk_divider),
		       &regs->lcdcon1);
		writel(S3CFB_LCDCON5_HWSWP | S3CFB_LCDCON5_FRM565,
		       &regs->lcdcon5);
		break;
	case 24:
		writel(S3CFB_LCDCON1_BPPMODE_TFT_24BPP |
		       S3CFB_LCDCON1_PNRMODE_TFT |
		       S3CFB_LCDCON1_CLKVAL(clk_divider),
		       &regs->lcdcon1);
		writel(S3CFB_LCDCON5_BPP24BL, &regs->lcdcon5);
		break;
	}

	writel(S3CFB_LCDCON2_LINEVAL(mode->yres - 1) |
	       S3CFB_LCDCON2_VBPD(mode->upper_margin - 1) |
	       S3CFB_LCDCON2_VFPD(mode->lower_margin - 1) |
	       S3CFB_LCDCON2_VSPW(mode->vsync_len - 1),
	       &regs->lcdcon2);

	writel(S3CFB_LCDCON3_HBPD(mode->right_margin - 1) |
	       S3CFB_LCDCON3_HFPD(mode->left_margin - 1) |
	       S3CFB_LCDCON3_HOZVAL(mode->xres - 1),
	       &regs->lcdcon3);

	writel(S3CFB_LCDCON4_HSPW(mode->hsync_len - 1),
	       &regs->lcdcon4);

	/* Write FB address. */
	writel(panel->frameAdrs >> 1, &regs->lcdsaddr1);
	writel((panel->frameAdrs +
	       (mode->xres * mode->yres * panel->gdfBytesPP)) >> 1,
	       &regs->lcdsaddr2);
	writel(mode->xres * bpp / 16, &regs->lcdsaddr3);

	/* Start the controller. */
	setbits_le32(&regs->lcdcon1, 1);
}
示例#2
0
static void print_cpu_speed(void)
{
	printf("FCLK = %u MHz, HCLK = %u MHz, PCLK = %u MHz, UCLK = %u MHz\n",
		get_FCLK()/MHZ, get_HCLK()/MHZ, get_PCLK()/MHZ, get_UCLK()/MHZ);
}
示例#3
0
文件: s3cfb_70.c 项目: jeehong/uboot
void lcd_ctrl_init_70(void *lcdbase)
{
	ulong freq_lcdclk; 
	ulong freq_Hclk;
	ulong fb_size;
	unsigned char nn;
	unsigned short *pp;
	int i;

	GPICON_REG = 0xaaaaaaaa;
	GPIPUD_REG = 0xaaaaaaaa;
	GPJCON_REG = 0xaaaaaaaa;
	GPJPUD_REG = 0xaaaaaaaa;

	lcd_disable();
	S3C_WINCON0 &= (~(S3C_WINCONx_ENWIN_F_ENABLE));

	MIFPCON_REG &= (~SEL_BYPASS_MASK);
	SPCON_REG &= (~LCD_SEL_MASK);
	SPCON_REG |= (RGB_IF_STYLE_MASK);

	freq_lcdclk = S3CFB_PIXEL_CLOCK;
	freq_Hclk = get_HCLK();

	nn = (unsigned char)(freq_Hclk / freq_lcdclk) - 1;
	if(freq_lcdclk < freq_Hclk/2)
	{
		S3C_VIDCON0 = S3C_VIDCON0_INTERLACE_F_PROGRESSIVE + S3C_VIDCON0_VIDOUT_RGB_IF + \
		        S3C_VIDCON0_PNRMODE_RGB_P + S3C_VIDCON0_CLKVALUP_ST_FRM + S3C_VIDCON0_CLKVAL_F(nn) + \
		        S3C_VIDCON0_CLKDIR_DIVIDED + S3C_VIDCON0_CLKSEL_F_HCLK;
	}else
	{
		S3C_VIDCON0 = S3C_VIDCON0_INTERLACE_F_PROGRESSIVE + S3C_VIDCON0_VIDOUT_RGB_IF + \
		        S3C_VIDCON0_PNRMODE_RGB_P + S3C_VIDCON0_CLKVALUP_ST_FRM + S3C_VIDCON0_CLKVAL_F(0) + \
		        S3C_VIDCON0_CLKDIR_DIRECTED  + S3C_VIDCON0_CLKSEL_F_HCLK;
	}

	nn = 0;
	if(S3CFB_IVCLK)
	{
		nn += S3C_VIDCON1_IVCLK_RISE_EDGE;
	}
	if(S3CFB_IHSYNC)
	{
		nn += S3C_VIDCON1_IHSYNC_INVERT;
	}
	if(S3CFB_IVSYNC)
	{
		nn += S3C_VIDCON1_IVSYNC_INVERT;
	}
	if(S3CFB_IVDEN)
	{
		nn += S3C_VIDCON1_IVDEN_INVERT;
	}
	S3C_VIDCON1 = (unsigned int)nn;
	S3C_VIDCON2 = 0;

	S3C_VIDTCON0 = S3C_VIDTCON0_VBPD(S3CFB_VBP - 1) | S3C_VIDTCON0_VFPD(S3CFB_VFP - 1) | S3C_VIDTCON0_VSPW(S3CFB_VSW - 1);
	S3C_VIDTCON1 = S3C_VIDTCON1_HBPD(S3CFB_HBP - 1) | S3C_VIDTCON1_HFPD(S3CFB_HFP -1) | S3C_VIDTCON1_HSPW(S3CFB_HSW - 1);
	S3C_VIDTCON2 = S3C_VIDTCON2_LINEVAL(S3CFB_VRES - 1) | S3C_VIDTCON2_HOZVAL(S3CFB_HRES - 1);

#if LCD_BPP == LCD_COLOR32
	S3C_WINCON0 = S3C_WINCONx_BPPMODE_F_24BPP_888;
	S3C_WINCON1 = S3C_WINCONx_BPPMODE_F_24BPP_888 | S3C_WINCONx_BLD_PIX_PIXEL;
#else
	S3C_WINCON0 = S3C_WINCONx_BPPMODE_F_16BPP_565 | S3C_WINCONx_HAWSWP_ENABLE;
	S3C_WINCON1 = S3C_WINCONx_BPPMODE_F_16BPP_565 | S3C_WINCONx_HAWSWP_ENABLE | S3C_WINCONx_BLD_PIX_PIXEL;
#endif

	S3C_WINCON2 = 0;
	S3C_WINCON3 = 0;
	S3C_WINCON4 = 0;

	S3C_VIDOSD0A = S3C_VIDOSDxA_OSD_LTX_F(0) + S3C_VIDOSDxA_OSD_LTY_F(0);
	S3C_VIDOSD0B = S3C_VIDOSDxB_OSD_RBX_F(S3CFB_HRES - 1) | S3C_VIDOSDxB_OSD_RBY_F(S3CFB_VRES - 1);
	S3C_VIDOSD0C = S3C_VIDOSD0C_OSDSIZE(S3CFB_HRES*S3CFB_VRES);

	S3C_VIDOSD1A = S3C_VIDOSDxA_OSD_LTX_F(0) + S3C_VIDOSDxA_OSD_LTY_F(0);
	S3C_VIDOSD1B = S3C_VIDOSDxB_OSD_RBX_F(S3CFB_HRES - 1) | S3C_VIDOSDxB_OSD_RBY_F(S3CFB_VRES - 1);
	S3C_VIDOSD1C = 0xDDD000;/*alpha blending*/
	S3C_VIDOSD1D = S3C_VIDOSD0C_OSDSIZE(S3CFB_HRES*S3CFB_VRES);

	S3C_VIDOSD2A = 0;
	S3C_VIDOSD2B = 0;
	S3C_VIDOSD2C = 0;
	S3C_VIDOSD2D = 0;
	S3C_VIDOSD3A = 0;
	S3C_VIDOSD3B = 0;
	S3C_VIDOSD3C = 0;
	S3C_VIDOSD4A = 0;
	S3C_VIDOSD4B = 0;
	S3C_VIDOSD4C = 0;

	fb_size = calc_fbsize();

	S3C_VIDW00ADD0B0 = virt_to_phys(lcdbase);
	S3C_VIDW00ADD0B1 = 0;
	S3C_VIDW01ADD0B0 = virt_to_phys(osd_frame_buffer);
	S3C_VIDW01ADD0B1 = 0;
	S3C_VIDW02ADD0 = 0;
	S3C_VIDW03ADD0 = 0;
	S3C_VIDW04ADD0 = 0;

	S3C_VIDW00ADD1B0 = virt_to_phys((unsigned int)(lcdbase) + fb_size);
	S3C_VIDW00ADD1B1 = 0;
	S3C_VIDW01ADD1B0 = virt_to_phys(osd_frame_buffer) + fb_size;
	S3C_VIDW01ADD1B1 = 0;
	S3C_VIDW02ADD1 = 0;
	S3C_VIDW03ADD1 = 0;
	S3C_VIDW04ADD1 = 0;

	S3C_VIDW00ADD2 = 0;//S3C_VIDWxxADD2_OFFSIZE_F(0) | (S3C_VIDWxxADD2_PAGEWIDTH_F(panel_info.vl_col*panel_info.vl_bpix/8));
	S3C_VIDW01ADD2 = 0;//S3C_VIDWxxADD2_OFFSIZE_F(0) | (S3C_VIDWxxADD2_PAGEWIDTH_F(panel_info.vl_col*panel_info.vl_bpix/8));
	S3C_VIDW02ADD2 = 0;
	S3C_VIDW03ADD2 = 0;
	S3C_VIDW04ADD2 = 0;

	S3C_W1KEYCON0  = S3C_WxKEYCON0_KEYBLEN_ENABLE | S3C_WxKEYCON0_KEYEN_F_ENABLE | S3C_WxKEYCON0_COMPKEY(0xFFFF);
	S3C_W1KEYCON1  = 0x00000000;/*color key*/

#if 1
	memset(lcdbase,0x00,fb_size*2);
#else
	pp = lcdbase;
	for(i=0;i< S3CFB_HRES * S3CFB_VRES;i++)
	{
		*pp = 0xf100;
		pp++;
	}
#endif
	lcd_enable();

	S3C_WINCON0 |= S3C_WINCONx_ENWIN_F_ENABLE;
	S3C_WINCON1 |= S3C_WINCONx_ENWIN_F_ENABLE;
	return (0);
}