C++ (Cpp) get_clock_tick_rate示例

示例#1

文件： time.c 项目： 0x0f/adam-kernel

static void __init pxa_timer_init(void)
{
	unsigned long clock_tick_rate = get_clock_tick_rate();

	OIER = 0;
	OSSR = OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3;

	set_oscr2ns_scale(clock_tick_rate);

	ckevt_pxa_osmr0.mult =
		div_sc(clock_tick_rate, NSEC_PER_SEC, ckevt_pxa_osmr0.shift);
	ckevt_pxa_osmr0.max_delta_ns =
		clockevent_delta2ns(0x7fffffff, &ckevt_pxa_osmr0);
	ckevt_pxa_osmr0.min_delta_ns =
		clockevent_delta2ns(MIN_OSCR_DELTA * 2, &ckevt_pxa_osmr0) + 1;
	ckevt_pxa_osmr0.cpumask = cpumask_of(0);

	cksrc_pxa_oscr0.mult =
		clocksource_hz2mult(clock_tick_rate, cksrc_pxa_oscr0.shift);

	setup_irq(IRQ_OST0, &pxa_ost0_irq);

	clocksource_register(&cksrc_pxa_oscr0);
	clockevents_register_device(&ckevt_pxa_osmr0);
}

示例#2

static void __init pxa_timer_init(void)
{
	unsigned long clock_tick_rate = get_clock_tick_rate();

	OIER = 0;
	OSSR = OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3;

	init_sched_clock(&cd, pxa_update_sched_clock, 32, clock_tick_rate);

	clockevents_calc_mult_shift(&ckevt_pxa_osmr0, clock_tick_rate, 4);
	ckevt_pxa_osmr0.max_delta_ns =
		clockevent_delta2ns(0x7fffffff, &ckevt_pxa_osmr0);
	ckevt_pxa_osmr0.min_delta_ns =
		clockevent_delta2ns(MIN_OSCR_DELTA * 2, &ckevt_pxa_osmr0) + 1;
	ckevt_pxa_osmr0.cpumask = cpumask_of(0);

	setup_irq(IRQ_OST0, &pxa_ost0_irq);

	clocksource_mmio_init((void *)&OSCR, "oscr0", clock_tick_rate, 200, 32,
		clocksource_mmio_readl_up);

#ifdef CONFIG_IPIPE
	tsc_info.freq = clock_tick_rate;
	__ipipe_tsc_register(&tsc_info);
#endif /* CONFIG_IPIPE */

	clockevents_register_device(&ckevt_pxa_osmr0);
}

示例#3

文件： generic.c 项目： 0-T-0/ps4-linux

/*
 * For non device-tree builds, keep legacy timer init
 */
void __init pxa_timer_init(void)
{
	if (cpu_is_pxa25x())
		pxa25x_clocks_init();
	if (cpu_is_pxa27x())
		pxa27x_clocks_init();
	if (cpu_is_pxa3xx())
		pxa3xx_clocks_init();
	pxa_timer_nodt_init(IRQ_OST0, io_p2v(0x40a00000),
			    get_clock_tick_rate());
}

示例#4

文件： time.c 项目： 0x000000FF/Linux4Edison

void __init pxa_timer_init(void)
{
	unsigned long clock_tick_rate = get_clock_tick_rate();

	writel_relaxed(0, OIER);
	writel_relaxed(OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3, OSSR);

	setup_sched_clock(pxa_read_sched_clock, 32, clock_tick_rate);

	ckevt_pxa_osmr0.cpumask = cpumask_of(0);

	setup_irq(IRQ_OST0, &pxa_ost0_irq);

	clocksource_mmio_init(OSCR, "oscr0", clock_tick_rate, 200, 32,
		clocksource_mmio_readl_up);
	clockevents_config_and_register(&ckevt_pxa_osmr0, clock_tick_rate,
		MIN_OSCR_DELTA * 2, 0x7fffffff);
}

示例#5

文件： sa1100_wdt.c 项目： openube/android_kernel_sony_c2305

static int __init sa1100dog_init(void)
{
	int ret;

	oscr_freq = get_clock_tick_rate();

	/*
	 * Read the reset status, and save it for later.  If
	 * we suspend, RCSR will be cleared, and the watchdog
	 * reset reason will be lost.
	 */
	boot_status = (reset_status & RESET_STATUS_WATCHDOG) ?
				WDIOF_CARDRESET : 0;
	pre_margin = oscr_freq * margin;

	ret = misc_register(&sa1100dog_miscdev);
	if (ret == 0)
		pr_info("SA1100/PXA2xx Watchdog Timer: timer margin %d sec\n",
			margin);
	return ret;
}

示例#6

文件： time.c 项目： 0709oNEY/at100-kernel

static void __init pxa_timer_init(void)
{
	unsigned long clock_tick_rate = get_clock_tick_rate();

	OIER = 0;
	OSSR = OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3;

	init_sched_clock(&cd, pxa_update_sched_clock, 32, clock_tick_rate);

	clocksource_calc_mult_shift(&cksrc_pxa_oscr0, clock_tick_rate, 4);
	clockevents_calc_mult_shift(&ckevt_pxa_osmr0, clock_tick_rate, 4);
	ckevt_pxa_osmr0.max_delta_ns =
		clockevent_delta2ns(0x7fffffff, &ckevt_pxa_osmr0);
	ckevt_pxa_osmr0.min_delta_ns =
		clockevent_delta2ns(MIN_OSCR_DELTA * 2, &ckevt_pxa_osmr0) + 1;
	ckevt_pxa_osmr0.cpumask = cpumask_of(0);

	setup_irq(IRQ_OST0, &pxa_ost0_irq);

	clocksource_register_hz(&cksrc_pxa_oscr0, clock_tick_rate);
	clockevents_register_device(&ckevt_pxa_osmr0);
}

示例#7

文件： time.c 项目： 12019/android_kernel_samsung_xcover

static void __init pxa_timer_init(void)
{
	unsigned long clock_tick_rate = get_clock_tick_rate();

	OIER = 0;
	OSSR = OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3;

	set_oscr2ns_scale(clock_tick_rate);

	clocksource_calc_mult_shift(&cksrc_pxa_oscr0, CLOCK_TICK_RATE, 4);
	clockevents_calc_mult_shift(&ckevt_pxa_osmr0, CLOCK_TICK_RATE, 4);
	ckevt_pxa_osmr0.max_delta_ns =
		clockevent_delta2ns(0x7fffffff, &ckevt_pxa_osmr0);
	ckevt_pxa_osmr0.min_delta_ns =
		clockevent_delta2ns(MIN_OSCR_DELTA * 2, &ckevt_pxa_osmr0) + 1;
	ckevt_pxa_osmr0.cpumask = cpumask_of(0);


	clocksource_register(&cksrc_pxa_oscr0);
	clockevents_register_device(&ckevt_pxa_osmr0);
	setup_irq(IRQ_OST0, &pxa_ost0_irq);

	rtc_calib_init();
}