static void dpll3_init_34xx(u32 sil_index, u32 clk_index)
{
struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
dpll_param *ptr = (dpll_param *) get_core_dpll_param();
void (*f_lock_pll) (u32, u32, u32, u32);
int xip_safe, p0, p1, p2, p3;
xip_safe = is_running_in_sram();
/* Moving to the right sysclk and ES rev base */
ptr = ptr + (3 * clk_index) + sil_index;
if (xip_safe) {
/*
* CORE DPLL
* sr32(CM_CLKSEL2_EMU) set override to work when asleep
*/
sr32(&prcm_base->clken_pll, 0, 3, PLL_FAST_RELOCK_BYPASS);
wait_on_value(ST_CORE_CLK, 0, &prcm_base->idlest_ckgen,
LDELAY);
/*
* For OMAP3 ES1.0 Errata 1.50, default value directly doesn't
* work. write another value and then default value.
*/
/* CM_CLKSEL1_EMU[DIV_DPLL3] */
sr32(&prcm_base->clksel1_emu, 16, 5, (CORE_M3X2 + 1)) ;
sr32(&prcm_base->clksel1_emu, 16, 5, CORE_M3X2);
/* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
sr32(&prcm_base->clksel1_pll, 27, 5, ptr->m2);
/* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
sr32(&prcm_base->clksel1_pll, 16, 11, ptr->m);
/* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
sr32(&prcm_base->clksel1_pll, 8, 7, ptr->n);
/* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
sr32(&prcm_base->clksel1_pll, 6, 1, 0);
/* SSI */
sr32(&prcm_base->clksel_core, 8, 4, CORE_SSI_DIV);
/* FSUSB */
sr32(&prcm_base->clksel_core, 4, 2, CORE_FUSB_DIV);
/* L4 */
sr32(&prcm_base->clksel_core, 2, 2, CORE_L4_DIV);
/* L3 */
sr32(&prcm_base->clksel_core, 0, 2, CORE_L3_DIV);
/* GFX */
sr32(&prcm_base->clksel_gfx, 0, 3, GFX_DIV);
/* RESET MGR */
sr32(&prcm_base->clksel_wkup, 1, 2, WKUP_RSM);
/* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
sr32(&prcm_base->clken_pll, 4, 4, ptr->fsel);
/* LOCK MODE */
sr32(&prcm_base->clken_pll, 0, 3, PLL_LOCK);
wait_on_value(ST_CORE_CLK, 1, &prcm_base->idlest_ckgen,
LDELAY);
} else if (is_running_in_flash()) {
/*
* if running from flash, jump to small relocated code
* area in SRAM.
*/
f_lock_pll = (void *) ((u32) &_end_vect - (u32) &_start +
SRAM_VECT_CODE);
p0 = readl(&prcm_base->clken_pll);
sr32(&p0, 0, 3, PLL_FAST_RELOCK_BYPASS);
/* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
sr32(&p0, 4, 4, ptr->fsel);
p1 = readl(&prcm_base->clksel1_pll);
/* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
sr32(&p1, 27, 5, ptr->m2);
/* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
sr32(&p1, 16, 11, ptr->m);
/* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
sr32(&p1, 8, 7, ptr->n);
/* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
sr32(&p1, 6, 1, 0);
p2 = readl(&prcm_base->clksel_core);
/* SSI */
sr32(&p2, 8, 4, CORE_SSI_DIV);
/* FSUSB */
sr32(&p2, 4, 2, CORE_FUSB_DIV);
/* L4 */
sr32(&p2, 2, 2, CORE_L4_DIV);
/* L3 */
sr32(&p2, 0, 2, CORE_L3_DIV);
p3 = (u32)&prcm_base->idlest_ckgen;
(*f_lock_pll) (p0, p1, p2, p3);
}
}
/******************************************************************************
* prcm_init() - inits clocks for PRCM as defined in clocks.h
* -- called from SRAM, or Flash (using temp SRAM stack).
*****************************************************************************/
void prcm_init(void)
{
void (*f_lock_pll) (u32, u32, u32, u32);
int xip_safe, p0, p1, p2, p3;
u32 osc_clk=0, sys_clkin_sel;
extern void *_end_vect, *_start;
u32 clk_index, sil_index=1;
dpll_param *dpll_param_p;
f_lock_pll =
(void *)((u32) & _end_vect - (u32) & _start + SRAM_VECT_CODE);
xip_safe = running_in_sram();
#ifdef CONFIG_3430VIRTIO
xip_safe = 1;
#endif
/* Gauge the input clock speed and find out the sys_clkin_sel
* value corresponding to the input clock.
*/
osc_clk = get_osc_clk_speed();
get_sys_clkin_sel(osc_clk, &sys_clkin_sel);
sr32(PRM_CLKSEL, 0, 3, sys_clkin_sel); /* set input crystal speed */
sr32(PRM_CLKSRC_CTRL, 6, 2, 1);/* input clock divider */
clk_index = sys_clkin_sel;
sr32(PRM_CLKSRC_CTRL, 0, 2, 0);/* Bypass mode: T2 inputs a square clock */
sil_index = get_silindex();
/* Unlock MPU DPLL (slows things down, and needed later) */
sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOW_POWER_BYPASS);
wait_on_value(BIT0, 0, CM_IDLEST_PLL_MPU, LDELAY);
/* Getting the base address of Core DPLL param table*/
dpll_param_p = (dpll_param *)get_core_dpll_param();
/* Moving it to the right sysclk and ES rev base */
dpll_param_p = dpll_param_p + MAX_SIL_INDEX*clk_index + sil_index;
if(xip_safe){
/* CORE DPLL */
/* sr32(CM_CLKSEL2_EMU) set override to work when asleep */
sr32(CM_CLKEN_PLL, 0, 3, PLL_FAST_RELOCK_BYPASS);
wait_on_value(BIT0, 0, CM_IDLEST_CKGEN, LDELAY);
/* For 3430 ES1.0 Errata 1.50, default value directly doesnt
work. write another value and then default value. */
sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2 + 1); /* m3x2 */
sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2); /* m3x2 */
sr32(CM_CLKSEL1_PLL, 27, 2, dpll_param_p->m2); /* Set M2 */
sr32(CM_CLKSEL1_PLL, 16, 11, dpll_param_p->m); /* Set M */
sr32(CM_CLKSEL1_PLL, 8, 7, dpll_param_p->n); /* Set N */
sr32(CM_CLKSEL1_PLL, 6, 1, 0); /* 96M Src */
sr32(CM_CLKSEL_CORE, 8, 4, CORE_SSI_DIV); /* ssi */
sr32(CM_CLKSEL_CORE, 4, 2, CORE_FUSB_DIV); /* fsusb ES1 only */
sr32(CM_CLKSEL_CORE, 2, 2, CORE_L4_DIV); /* l4 */
sr32(CM_CLKSEL_CORE, 0, 2, CORE_L3_DIV); /* l3 */
sr32(CM_CLKSEL_GFX, 0, 3, GFX_DIV); /* gfx */
sr32(CM_CLKSEL_WKUP, 1, 2, WKUP_RSM); /* reset mgr */
#ifndef CONFIG_OMAP36XX
sr32(CM_CLKEN_PLL, 4, 4, dpll_param_p->fsel); /* FREQSEL */
#endif
sr32(CM_CLKEN_PLL, 0, 3, PLL_LOCK); /* lock mode */
wait_on_value(BIT0, 1, CM_IDLEST_CKGEN, LDELAY);
} else if(running_in_flash()){
/* if running from flash, jump to small relocated code area in SRAM.*/
p0 = __raw_readl(CM_CLKEN_PLL);
sr32((u32)&p0, 0, 3, PLL_FAST_RELOCK_BYPASS);
#ifndef CONFIG_OMAP36XX
sr32((u32)&p0, 4, 4, dpll_param_p->fsel); /* FREQSEL */
#endif
p1 = __raw_readl(CM_CLKSEL1_PLL);
sr32((u32)&p1, 27, 2, dpll_param_p->m2); /* Set M2 */
sr32((u32)&p1, 16, 11, dpll_param_p->m); /* Set M */
sr32((u32)&p1, 8, 7, dpll_param_p->n); /* Set N */
sr32((u32)&p1, 6, 1, 0); /* set source for 96M */
p2 = __raw_readl(CM_CLKSEL_CORE);
sr32((u32)&p2, 8, 4, CORE_SSI_DIV); /* ssi */
sr32((u32)&p2, 4, 2, CORE_FUSB_DIV); /* fsusb ES1 only*/
sr32((u32)&p2, 2, 2, CORE_L4_DIV); /* l4 */
sr32((u32)&p2, 0, 2, CORE_L3_DIV); /* l3 */
p3 = CM_IDLEST_CKGEN;
(*f_lock_pll) (p0, p1, p2, p3);
}
#ifdef CONFIG_OMAP36XX
per_dpll_init_36XX(clk_index);
iva_dpll_init_36XX(clk_index, sil_index);
mpu_dpll_init_36XX(clk_index, sil_index);
#else
per_dpll_init_34XX(clk_index);
iva_dpll_init_34XX(clk_index, sil_index);
mpu_dpll_init_34XX(clk_index, sil_index);
#endif
/* Set up GPTimers to sys_clk source only */
sr32(CM_CLKSEL_PER, 0, 8, 0xff);
sr32(CM_CLKSEL_WKUP, 0, 1, 1);
sdelay(5000);
}
static void dpll3_init_34xx(u32 sil_index, u32 clk_index)
{
struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
dpll_param *ptr = (dpll_param *) get_core_dpll_param();
void (*f_lock_pll) (u32, u32, u32, u32);
int xip_safe, p0, p1, p2, p3;
xip_safe = is_running_in_sram();
/* Moving to the right sysclk and ES rev base */
ptr = ptr + (3 * clk_index) + sil_index;
if (xip_safe) {
/*
* CORE DPLL
*/
clrsetbits_le32(&prcm_base->clken_pll,
0x00000007, PLL_FAST_RELOCK_BYPASS);
wait_on_value(ST_CORE_CLK, 0, &prcm_base->idlest_ckgen,
LDELAY);
/*
* For OMAP3 ES1.0 Errata 1.50, default value directly doesn't
* work. write another value and then default value.
*/
/* CM_CLKSEL1_EMU[DIV_DPLL3] */
clrsetbits_le32(&prcm_base->clksel1_emu,
0x001F0000, (CORE_M3X2 + 1) << 16) ;
clrsetbits_le32(&prcm_base->clksel1_emu,
0x001F0000, CORE_M3X2 << 16);
/* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
clrsetbits_le32(&prcm_base->clksel1_pll,
0xF8000000, ptr->m2 << 27);
/* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
clrsetbits_le32(&prcm_base->clksel1_pll,
0x07FF0000, ptr->m << 16);
/* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
clrsetbits_le32(&prcm_base->clksel1_pll,
0x00007F00, ptr->n << 8);
/* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
clrbits_le32(&prcm_base->clksel1_pll, 0x00000040);
/* SSI */
clrsetbits_le32(&prcm_base->clksel_core,
0x00000F00, CORE_SSI_DIV << 8);
/* FSUSB */
clrsetbits_le32(&prcm_base->clksel_core,
0x00000030, CORE_FUSB_DIV << 4);
/* L4 */
clrsetbits_le32(&prcm_base->clksel_core,
0x0000000C, CORE_L4_DIV << 2);
/* L3 */
clrsetbits_le32(&prcm_base->clksel_core,
0x00000003, CORE_L3_DIV);
/* GFX */
clrsetbits_le32(&prcm_base->clksel_gfx,
0x00000007, GFX_DIV);
/* RESET MGR */
clrsetbits_le32(&prcm_base->clksel_wkup,
0x00000006, WKUP_RSM << 1);
/* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
clrsetbits_le32(&prcm_base->clken_pll,
0x000000F0, ptr->fsel << 4);
/* LOCK MODE */
clrsetbits_le32(&prcm_base->clken_pll,
0x00000007, PLL_LOCK);
wait_on_value(ST_CORE_CLK, 1, &prcm_base->idlest_ckgen,
LDELAY);
} else if (is_running_in_flash()) {
/*
* if running from flash, jump to small relocated code
* area in SRAM.
*/
f_lock_pll = (void *) (SRAM_CLK_CODE);
p0 = readl(&prcm_base->clken_pll);
clrsetbits_le32(&p0, 0x00000007, PLL_FAST_RELOCK_BYPASS);
/* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
clrsetbits_le32(&p0, 0x000000F0, ptr->fsel << 4);
p1 = readl(&prcm_base->clksel1_pll);
/* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
clrsetbits_le32(&p1, 0xF8000000, ptr->m2 << 27);
/* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
clrsetbits_le32(&p1, 0x07FF0000, ptr->m << 16);
/* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
clrsetbits_le32(&p1, 0x00007F00, ptr->n << 8);
/* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
clrbits_le32(&p1, 0x00000040);
p2 = readl(&prcm_base->clksel_core);
/* SSI */
clrsetbits_le32(&p2, 0x00000F00, CORE_SSI_DIV << 8);
/* FSUSB */
clrsetbits_le32(&p2, 0x00000030, CORE_FUSB_DIV << 4);
/* L4 */
clrsetbits_le32(&p2, 0x0000000C, CORE_L4_DIV << 2);
/* L3 */
clrsetbits_le32(&p2, 0x00000003, CORE_L3_DIV);
p3 = (u32)&prcm_base->idlest_ckgen;
(*f_lock_pll) (p0, p1, p2, p3);
}
}
static dpll_param *_get_core_dpll(int clk_index, int sil_index)
{
dpll_param *ret = (dpll_param *)get_core_dpll_param();
ret += (MAX_SIL_INDEX * clk_index) + sil_index;
return ret;
}
