int checkboard (void) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); /* PCI slot in USER bits CSR[6:7] by convention. */ uint pci_slot = get_pci_slot (); uint cpu_board_rev = get_cpu_board_revision (); printf ("Board: CDS Version 0x%02x, PCI Slot %d\n", get_board_version (), pci_slot); printf ("CPU Board Revision %d.%d (0x%04x)\n", MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev), MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev); /* * Initialize local bus. */ local_bus_init (); /* * Hack TSEC 3 and 4 IO voltages. */ gur->tsec34ioovcr = 0xe7e0; /* 1110 0111 1110 0xxx */ ecm->eedr = 0xffffffff; /* clear ecm errors */ ecm->eeer = 0xffffffff; /* enable ecm errors */ return 0; }
int checkboard (void) { volatile immap_t *immap = (immap_t *) CFG_CCSRBAR; volatile ccsr_gur_t *gur = &immap->im_gur; /* PCI slot in USER bits CSR[6:7] by convention. */ uint pci_slot = get_pci_slot (); uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */ uint pci1_32 = gur->pordevsr & 0x10000; /* PORDEVSR[15] */ uint pci1_clk_sel = gur->porpllsr & 0x8000; /* PORPLLSR[16] */ uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */ uint pci1_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */ uint cpu_board_rev = get_cpu_board_revision (); printf ("Board: CDS Version 0x%02x, PCI Slot %d\n", get_board_version (), pci_slot); printf ("CPU Board Revision %d.%d (0x%04x)\n", MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev), MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev); printf (" PCI1: %d bit, %s MHz, %s\n", (pci1_32) ? 32 : 64, (pci1_speed == 33000000) ? "33" : (pci1_speed == 66000000) ? "66" : "unknown", pci1_clk_sel ? "sync" : "async"); if (pci_dual) { printf (" PCI2: 32 bit, 66 MHz, %s\n", pci2_clk_sel ? "sync" : "async"); } else { printf (" PCI2: disabled\n"); } /* * Initialize local bus. */ local_bus_init (); return 0; }
int checkboard (void) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); char buf[32]; /* PCI slot in USER bits CSR[6:7] by convention. */ uint pci_slot = get_pci_slot (); uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */ uint pci1_32 = gur->pordevsr & 0x10000; /* PORDEVSR[15] */ uint pci1_clk_sel = gur->porpllsr & 0x8000; /* PORPLLSR[16] */ uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */ uint pci1_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */ uint cpu_board_rev = get_cpu_board_revision (); printf ("Board: CDS Version 0x%02x, PCI Slot %d\n", get_board_version (), pci_slot); printf ("CPU Board Revision %d.%d (0x%04x)\n", MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev), MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev); printf("PCI1: %d bit, %s MHz, %s\n", (pci1_32) ? 32 : 64, strmhz(buf, pci1_speed), pci1_clk_sel ? "sync" : "async"); if (pci_dual) { printf("PCI2: 32 bit, 66 MHz, %s\n", pci2_clk_sel ? "sync" : "async"); } else { printf("PCI2: disabled\n"); } /* * Initialize local bus. */ local_bus_init (); return 0; }
int checkboard (void) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); /* PCI slot in USER bits CSR[6:7] by convention. */ uint pci_slot = get_pci_slot (); uint cpu_board_rev = get_cpu_board_revision (); uint svr; printf ("Board: CDS Version 0x%02x, PCI Slot %d\n", get_board_version (), pci_slot); printf ("CPU Board Revision %d.%d (0x%04x)\n", MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev), MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev); /* * Initialize local bus. */ local_bus_init (); svr = get_svr(); /* * Fix CPU2 errata: A core hang possible while executing a * msync instruction and a snoopable transaction from an I/O * master tagged to make quick forward progress is present. * Fixed in Silicon Rev.2.1 */ if (!(SVR_MAJ(svr) >= 2 && SVR_MIN(svr) >= 1)) ecm->eebpcr |= (1 << 16); /* * Hack TSEC 3 and 4 IO voltages. */ gur->tsec34ioovcr = 0xe7e0; /* 1110 0111 1110 0xxx */ ecm->eedr = 0xffffffff; /* clear ecm errors */ ecm->eeer = 0xffffffff; /* enable ecm errors */ return 0; }
/* * Initialize SDRAM memory on the Local Bus. */ void sdram_init(void) { #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM) uint idx; volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; uint cpu_board_rev; uint lsdmr_common; puts(" SDRAM: "); print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); /* * Setup SDRAM Base and Option Registers */ lbc->or2 = CONFIG_SYS_OR2_PRELIM; asm("msync"); lbc->br2 = CONFIG_SYS_BR2_PRELIM; asm("msync"); lbc->lbcr = CONFIG_SYS_LBC_LBCR; asm("msync"); lbc->lsrt = CONFIG_SYS_LBC_LSRT; lbc->mrtpr = CONFIG_SYS_LBC_MRTPR; asm("msync"); /* * Determine which address lines to use baed on CPU board rev. */ cpu_board_rev = get_cpu_board_revision(); lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON; if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_0) { lsdmr_common |= LSDMR_BSMA1617; } else if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_1) { lsdmr_common |= LSDMR_BSMA1516; } else { /* * Assume something unable to identify itself is * really old, and likely has lines 16/17 mapped. */ lsdmr_common |= LSDMR_BSMA1617; } /* * Issue PRECHARGE ALL command. */ lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL; asm("sync;msync"); *sdram_addr = 0xff; ppcDcbf((unsigned long) sdram_addr); udelay(100); /* * Issue 8 AUTO REFRESH commands. */ for (idx = 0; idx < 8; idx++) { lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH; asm("sync;msync"); *sdram_addr = 0xff; ppcDcbf((unsigned long) sdram_addr); udelay(100); } /* * Issue 8 MODE-set command. */ lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW; asm("sync;msync"); *sdram_addr = 0xff; ppcDcbf((unsigned long) sdram_addr); udelay(100); /* * Issue NORMAL OP command. */ lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL; asm("sync;msync"); *sdram_addr = 0xff; ppcDcbf((unsigned long) sdram_addr); udelay(200); /* Overkill. Must wait > 200 bus cycles */ #endif /* enable SDRAM init */ }
/* * Initialize SDRAM memory on the Local Bus. */ void sdram_init(void) { #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM) uint idx; volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; uint cpu_board_rev; uint lsdmr_common; puts(" SDRAM: "); print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); /* * Setup SDRAM Base and Option Registers */ lbc->or2 = CONFIG_SYS_OR2_PRELIM; asm("msync"); lbc->br2 = CONFIG_SYS_BR2_PRELIM; asm("msync"); lbc->lbcr = CONFIG_SYS_LBC_LBCR; asm("msync"); lbc->lsrt = CONFIG_SYS_LBC_LSRT; lbc->mrtpr = CONFIG_SYS_LBC_MRTPR; asm("msync"); /* * MPC8548 uses "new" 15-16 style addressing. */ cpu_board_rev = get_cpu_board_revision(); lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON; lsdmr_common |= CONFIG_SYS_LBC_LSDMR_BSMA1516; /* * Issue PRECHARGE ALL command. */ lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_PCHALL; asm("sync;msync"); *sdram_addr = 0xff; ppcDcbf((unsigned long) sdram_addr); udelay(100); /* * Issue 8 AUTO REFRESH commands. */ for (idx = 0; idx < 8; idx++) { lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_ARFRSH; asm("sync;msync"); *sdram_addr = 0xff; ppcDcbf((unsigned long) sdram_addr); udelay(100); } /* * Issue 8 MODE-set command. */ lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_MRW; asm("sync;msync"); *sdram_addr = 0xff; ppcDcbf((unsigned long) sdram_addr); udelay(100); /* * Issue NORMAL OP command. */ lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_NORMAL; asm("sync;msync"); *sdram_addr = 0xff; ppcDcbf((unsigned long) sdram_addr); udelay(200); /* Overkill. Must wait > 200 bus cycles */ #endif /* enable SDRAM init */ }