ir_node *be_new_Perm(arch_register_class_t const *const cls, ir_node *const block, int const n, ir_node *const *const in) { ir_graph *irg = get_irn_irg(block); ir_node *irn = new_ir_node(NULL, irg, block, op_be_Perm, mode_T, n, in); init_node_attr(irn, n, arch_irn_flags_none); be_node_attr_t *attr = (be_node_attr_t*)get_irn_generic_attr(irn); attr->exc.pin_state = op_pin_state_pinned; for (int i = 0; i < n; ++i) { const ir_node *input = in[i]; const arch_register_req_t *req = arch_get_irn_register_req(input); if (req->width == 1) { be_node_set_register_req_in(irn, i, cls->class_req); arch_set_irn_register_req_out(irn, i, cls->class_req); } else { arch_register_req_t *const new_req = allocate_reg_req(irg); new_req->cls = cls; new_req->width = req->width; new_req->aligned = req->aligned; be_node_set_register_req_in(irn, i, new_req); arch_set_irn_register_req_out(irn, i, new_req); } } return irn; }
static void sparc_set_attr_imm(ir_node *res, ir_entity *entity, int32_t immediate_value) { sparc_attr_t *attr = (sparc_attr_t*)get_irn_generic_attr(res); attr->immediate_value_entity = entity; attr->immediate_value = immediate_value; arch_add_irn_flags(res, (arch_irn_flags_t)sparc_arch_irn_flag_immediate_form); }
void init_ia32_return_attributes(ir_node *node, uint16_t pop) { ia32_return_attr_t *attr = (ia32_return_attr_t*)get_irn_generic_attr(node); #ifndef NDEBUG attr->attr.attr_type |= IA32_ATTR_ia32_return_attr_t; #endif attr->pop = pop; }
static void init_ia32_climbframe_attributes(ir_node *res, unsigned count) { ia32_climbframe_attr_t *attr = (ia32_climbframe_attr_t*)get_irn_generic_attr(res); #ifndef NDEBUG attr->attr.attr_type |= IA32_ATTR_ia32_climbframe_attr_t; #endif attr->count = count; }
void init_ia32_copyb_attributes(ir_node *res, unsigned size) { ia32_copyb_attr_t *attr = (ia32_copyb_attr_t*)get_irn_generic_attr(res); #ifndef NDEBUG attr->attr.attr_type |= IA32_ATTR_ia32_copyb_attr_t; #endif attr->size = size; }
void init_ia32_immediate_attributes(ir_node *res, x86_imm32_t const *const imm) { ia32_immediate_attr_t *attr = (ia32_immediate_attr_t*)get_irn_generic_attr(res); #ifndef NDEBUG attr->attr.attr_type |= IA32_ATTR_ia32_immediate_attr_t; #endif attr->imm = *imm; }
void init_ia32_condcode_attributes(ir_node *res, x86_condition_code_t cc) { ia32_condcode_attr_t *attr = (ia32_condcode_attr_t*)get_irn_generic_attr(res); #ifndef NDEBUG attr->attr.attr_type |= IA32_ATTR_ia32_condcode_attr_t; #endif attr->condition_code = cc; }
void init_ia32_call_attributes(ir_node* res, uint8_t pop, uint8_t n_reg_results) { ia32_call_attr_t *attr = (ia32_call_attr_t*)get_irn_generic_attr(res); #ifndef NDEBUG attr->attr.attr_type |= IA32_ATTR_ia32_call_attr_t; #endif attr->pop = pop; attr->n_reg_results = n_reg_results; }
void init_ia32_switch_attributes(ir_node *node, ir_switch_table const *const table, ir_entity const *const table_entity) { ia32_switch_attr_t *attr = (ia32_switch_attr_t*) get_irn_generic_attr(node); #ifndef NDEBUG attr->attr.attr_type |= IA32_ATTR_ia32_switch_attr_t; #endif be_switch_attr_init(node, &attr->swtch, table, table_entity); }
static void init_ia32_call_attributes(ir_node* res, unsigned pop, ir_type* call_tp) { ia32_call_attr_t *attr = (ia32_call_attr_t*)get_irn_generic_attr(res); #ifndef NDEBUG attr->attr.attr_type |= IA32_ATTR_ia32_call_attr_t; #endif attr->pop = pop; attr->call_tp = call_tp; }
ir_node *be_new_AnyVal(ir_node *block, const arch_register_class_t *cls) { ir_graph *irg = get_irn_irg(block); ir_mode *mode = cls->mode; ir_node *res = new_ir_node(NULL, irg, block, op_be_AnyVal, mode, 0, NULL); init_node_attr(res, 1, arch_irn_flags_none); arch_set_irn_register_req_out(res, 0, cls->class_req); be_node_attr_t *attr = (be_node_attr_t*)get_irn_generic_attr(res); attr->exc.pin_state = op_pin_state_floats; return res; }
static void init_ia32_switch_attributes(ir_node *node, const ir_switch_table *table) { ia32_switch_attr_t *attr = (ia32_switch_attr_t*) get_irn_generic_attr(node); #ifndef NDEBUG attr->attr.attr_type |= IA32_ATTR_ia32_switch_attr_t; #endif attr->table = table; be_foreach_out(node, o) { arch_set_irn_register_req_out(node, o, arch_no_register_req); }
ir_node *be_new_Asm(dbg_info *const dbgi, ir_node *const block, int const n_ins, ir_node **const ins, arch_register_req_t const **const in_reqs, int const n_outs, ident *const text, void *const operands) { ir_graph *const irg = get_irn_irg(block); ir_node *const asmn = new_ir_node(dbgi, irg, block, op_be_Asm, mode_T, n_ins, ins); be_info_init_irn(asmn, arch_irn_flags_none, in_reqs, n_outs); be_asm_attr_t *const attr = (be_asm_attr_t*)get_irn_generic_attr(asmn); attr->text = text; attr->operands = operands; return asmn; }
ir_node *be_new_Relocation(dbg_info *const dbgi, ir_graph *const irg, unsigned const kind, ir_entity *const entity, ir_mode *const mode) { ir_node *const block = get_irg_start_block(irg); ir_node *const node = new_ir_node(dbgi, irg, block, op_be_Relocation, mode, 0, NULL); be_relocation_attr_t *const attr = (be_relocation_attr_t*)get_irn_generic_attr(node); attr->entity = entity; attr->kind = kind; ir_node *const optimized = optimize_node(node); return optimized; }
ir_node *be_new_MemPerm(ir_node *const block, int n, ir_node *const *const in) { ir_graph *const irg = get_irn_irg(block); ir_node *const irn = new_ir_node(NULL, irg, block, op_be_MemPerm, mode_T, n, in); init_node_attr(irn, n, arch_irn_flags_none); be_memperm_attr_t *attr = (be_memperm_attr_t*)get_irn_generic_attr(irn); attr->in_entities = OALLOCNZ(get_irg_obstack(irg), ir_entity*, n); attr->out_entities = OALLOCNZ(get_irg_obstack(irg), ir_entity*, n); attr->offset = 0; return irn; }
static void set_copy_info(ir_node *const irn, ir_graph *const irg, ir_node *const op, arch_irn_flags_t const flags) { init_node_attr(irn, 1, flags); be_node_attr_t *const attr = (be_node_attr_t*)get_irn_generic_attr(irn); attr->exc.pinned = false; arch_register_req_t const *const op_req = arch_get_irn_register_req(op); arch_register_class_t const *const cls = op_req->cls; be_node_set_register_req_in(irn, 0, cls->class_req); arch_register_req_t *const out_req = be_create_cls_req(irg, cls, op_req->width); out_req->should_be_same = 1U << 0; arch_set_irn_register_req_out(irn, 0, out_req); }
ir_node *be_new_Keep(ir_node *const block, int const n, ir_node *const *const in) { ir_graph *irg = get_irn_irg(block); ir_node *res = new_ir_node(NULL, irg, block, op_be_Keep, mode_ANY, n, in); init_node_attr(res, 1, arch_irn_flag_schedule_first); be_node_attr_t *attr = (be_node_attr_t*) get_irn_generic_attr(res); attr->exc.pinned = true; for (int i = 0; i < n; ++i) { arch_register_req_t const *const req = arch_get_irn_register_req(in[i]); be_node_set_register_req_in(res, i, req->cls->class_req); } keep_alive(res); return res; }
ir_node *be_new_IncSP(ir_node *bl, ir_node *old_sp, int offset, bool no_align) { arch_register_class_t const *const cls = arch_get_irn_register_req(old_sp)->cls; ir_graph *irg = get_irn_irg(bl); ir_node *in[] = { old_sp }; ir_node *irn = new_ir_node(NULL, irg, bl, op_be_IncSP, cls->mode, ARRAY_SIZE(in), in); init_node_attr(irn, 1, arch_irn_flags_none); be_incsp_attr_t *a = (be_incsp_attr_t*)get_irn_generic_attr(irn); a->offset = offset; a->no_align = no_align; /* Set output constraint to stack register. */ be_node_set_register_req_in(irn, 0, cls->class_req); arch_copy_irn_out_info(irn, 0, old_sp); return irn; }
ir_node *be_new_IncSP(const arch_register_t *sp, ir_node *bl, ir_node *old_sp, int offset, unsigned align) { ir_graph *irg = get_irn_irg(bl); ir_node *in[] = { old_sp }; ir_node *irn = new_ir_node(NULL, irg, bl, op_be_IncSP, sp->cls->mode, ARRAY_SIZE(in), in); init_node_attr(irn, 1, arch_irn_flags_none); be_incsp_attr_t *a = (be_incsp_attr_t*)get_irn_generic_attr(irn); a->offset = offset; a->align = align; a->base.exc.pinned = true; /* Set output constraint to stack register. */ be_node_set_register_req_in(irn, 0, sp->cls->class_req); arch_copy_irn_out_info(irn, 0, old_sp); return irn; }
ir_node *be_new_Perm(ir_node *const block, int const n, ir_node *const *const in) { ir_graph *const irg = get_irn_irg(block); ir_node *const irn = new_ir_node(NULL, irg, block, op_be_Perm, mode_T, n, in); init_node_attr(irn, n, arch_irn_flags_none); be_node_attr_t *const attr = (be_node_attr_t*)get_irn_generic_attr(irn); attr->exc.pinned = true; for (int i = 0; i < n; ++i) { arch_register_req_t const *const in_req = arch_get_irn_register_req(in[i]); arch_register_req_t const *const slot_req = in_req->width == 1 ? in_req->cls->class_req : be_create_cls_req(irg, in_req->cls, in_req->width); be_node_set_register_req_in( irn, i, slot_req); arch_set_irn_register_req_out(irn, i, slot_req); } return irn; }
static void set_copy_info(ir_node *const irn, ir_graph *const irg, ir_node *const op, arch_irn_flags_t const flags) { init_node_attr(irn, 1, flags); be_node_attr_t *const attr = (be_node_attr_t*)get_irn_generic_attr(irn); attr->exc.pin_state = op_pin_state_floats; arch_register_req_t const *const op_req = arch_get_irn_register_req(op); arch_register_class_t const *const cls = op_req->cls; be_node_set_register_req_in(irn, 0, cls->class_req); arch_register_req_t *const out_req = allocate_reg_req(irg); out_req->cls = cls; out_req->should_be_same = 1U << 0; out_req->aligned = op_req->aligned; out_req->width = op_req->width; arch_set_irn_register_req_out(irn, 0, out_req); }
void be_set_MemPerm_offset(ir_node *irn, int offset) { assert(be_is_MemPerm(irn)); be_memperm_attr_t *attr = (be_memperm_attr_t*)get_irn_generic_attr(irn); attr->offset = offset; }
arm_CopyB_attr_t *get_arm_CopyB_attr(ir_node *node) { assert(is_arm_CopyB(node)); return (arm_CopyB_attr_t*)get_irn_generic_attr(node); }
sparc_asm_attr_t *get_sparc_asm_attr(ir_node *node) { assert(is_sparc_ASM(node)); return (sparc_asm_attr_t*)get_irn_generic_attr(node); }
arm_farith_attr_t *get_arm_farith_attr(ir_node *node) { assert(has_farith_attr(node)); return (arm_farith_attr_t*)get_irn_generic_attr(node); }
static arm_fConst_attr_t *get_arm_fConst_attr(ir_node *node) { assert(is_arm_fConst(node)); return (arm_fConst_attr_t*)get_irn_generic_attr(node); }
arm_Address_attr_t *get_arm_Address_attr(ir_node *node) { assert(arm_has_address_attr(node)); return (arm_Address_attr_t*)get_irn_generic_attr(node); }
void be_set_IncSP_offset(ir_node *irn, int offset) { assert(be_is_IncSP(irn)); be_incsp_attr_t *a = (be_incsp_attr_t*)get_irn_generic_attr(irn); a->offset = offset; }
arm_SwitchJmp_attr_t *get_arm_SwitchJmp_attr(ir_node *node) { assert(is_arm_SwitchJmp(node)); return (arm_SwitchJmp_attr_t*)get_irn_generic_attr(node); }
ia32_attr_t *get_ia32_attr(ir_node *node) { assert(is_ia32_irn(node) && "need ia32 node to get ia32 attributes"); return (ia32_attr_t *)get_irn_generic_attr(node); }