/*
* boot and execute the linux kernel
* r0 = must contain a zero or else the kernel loops
* r1 = architecture type
* r2 = physical address of tagged list in system ram
*/
static int bootlinux(int argc, char ** argv)
{
s32_t ret;
s32_t linux_mach_type, linux_kernel, linux_tag_placement;
struct machine * mach = get_machine();
struct tag * params;
s8_t *p;
s32_t i;
if(argc != 5)
{
printk("usage:\r\n bootlinux <KERNEL ADDR> <PARAM ADDR> <MACH TYPE> <COMMAND LINE>\r\n");
return -1;
}
if(!mach)
{
printk("can not get machine information.\r\n");
return -1;
}
linux_kernel = strtoul((const char *)argv[1], NULL, 0);
linux_tag_placement = strtoul((const char *)argv[2], NULL, 0);
linux_mach_type = strtoul((const char *)argv[3], NULL, 0);
/* setup linux kernel boot params */
params = (struct tag *)linux_tag_placement;
/* first tag */
params->hdr.tag = ATAG_CORE;
params->hdr.size = tag_size(tag_core);
params->u.core.flags = 0;
params->u.core.pagesize = 0;
params->u.core.rootdev = 0;
params = tag_next(params);
/* memory tags */
for(i = 0; i < ARRAY_SIZE(mach->res.mem_banks); i++)
{
if( (mach->res.mem_banks[i].start == 0) && (mach->res.mem_banks[i].end == 0) )
break;
params->hdr.tag = ATAG_MEM;
params->hdr.size = tag_size(tag_mem32);
params->u.mem.start = (u32_t)mach->res.mem_banks[i].start;
params->u.mem.size = (u32_t)(mach->res.mem_banks[i].end - mach->res.mem_banks[i].start + 1);
params = tag_next(params);
}
/* command line tags */
p = (s8_t *)argv[4];
if(p && strlen((const char *)p))
{
params->hdr.tag = ATAG_CMDLINE;
params->hdr.size = (sizeof (struct tag_header) + strlen((char *)p) + 1 + 4) >> 2;
strcpy((char *)(params->u.cmdline.cmdline), (char *)p);
params = tag_next (params);
}
static __init void realview_clk_init(void)
{
u32_t i;
u64_t xtal = 0;
/* get system xtal */
if(get_machine() != 0)
xtal = (get_machine())->res.xtal;
if(xtal == 0)
xtal = 12*1000*1000;
/* setup clock arrays */
realview_setup_clocks(xtal);
/* register clocks to system */
for(i=0; i< ARRAY_SIZE(realview_clocks); i++)
{
if(!clk_register(&realview_clocks[i]))
{
LOG_E("failed to register clock '%s'", realview_clocks[i].name);
}
}
}
int fencins(const std::map<std::string,Flag> flags, std::istream &input_stream){
std::set<std::string> used_flags =
{"a","k","cegar","max-refinements","max-solutions","rff","fmin","fence-cost",
"dismiss-fence","fence-full-branch-only"};
inform_ignore(used_flags.begin(),used_flags.end(),flags);
std::unique_ptr<Machine> machine(get_machine(flags,input_stream));
int max_refinements = -1;
if(flags.count("max-refinements")){
std::stringstream ss(flags.find("max-refinements")->second.argument);
if(!(ss >> max_refinements) || !ss.eof()){
std::cerr << "Invalid value '" << flags.find("max-refinements")->second.argument << "' given for max-refinements.\n";
return 1;
}
}
/* Initialise the struct args */
static void init_args (struct args *args)
{
/* Most of the fields initialise to 0 */
memset (args, 0, sizeof (*args));
/* Some do not */
args->w_octalish = 1;
args->sources = malloc (LIST_ARG_MAX * sizeof (*args->sources));
if (args->sources == NULL) error_errno ();
free_on_exit (args->sources);
memset (args->sources, 0, LIST_ARG_MAX * sizeof (*args->sources));
args->machine = get_machine ();
args->libs = malloc (LIST_ARG_MAX * sizeof (*args->libs));
if (args->libs == NULL) error_errno ();
free_on_exit (args->libs);
memset (args->libs, 0, LIST_ARG_MAX * sizeof (*args->libs));
args->lib_dirs = malloc (LIST_ARG_MAX * sizeof (*args->lib_dirs));
if (args->lib_dirs == NULL) error_errno ();
free_on_exit (args->lib_dirs);
memset (args->lib_dirs, 0, LIST_ARG_MAX * sizeof (*args->lib_dirs));
args->pkg_dirs = malloc (LIST_ARG_MAX * sizeof (*args->pkg_dirs));
if (args->pkg_dirs == NULL) error_errno ();
free_on_exit (args->pkg_dirs);
memset (args->pkg_dirs, 0, LIST_ARG_MAX * sizeof (*args->pkg_dirs));
args->llc_opts = malloc (LIST_ARG_MAX * sizeof (*args->llc_opts));
if (args->llc_opts == NULL) error_errno ();
free_on_exit (args->llc_opts);
memset (args->llc_opts, 0, LIST_ARG_MAX * sizeof (*args->llc_opts));
args->as_opts = malloc (LIST_ARG_MAX * sizeof (*args->as_opts));
if (args->as_opts == NULL) error_errno ();
free_on_exit (args->as_opts);
memset (args->as_opts, 0, LIST_ARG_MAX * sizeof (*args->as_opts));
args->ld_opts = malloc (LIST_ARG_MAX * sizeof (*args->ld_opts));
if (args->ld_opts == NULL) error_errno ();
free_on_exit (args->ld_opts);
memset (args->ld_opts, 0, LIST_ARG_MAX * sizeof (*args->ld_opts));
}
size_t volk_gnsssdr_get_alignment(void)
{
get_machine(); //ensures alignment is set
return __alignment;
}
void VipsBitReachability::test(){
std::function<Machine*(std::string)> get_machine =
[](std::string rmm){
std::stringstream ss(rmm);
PPLexer lex(ss);
return new Machine(Parser::p_test(lex));
};
/* Test 1: Dekker */
{
Machine *m = get_machine
("forbidden CS CS\n"
"data\n"
" x = 0 : [0:1]\n"
" y = 0 : [0:1]\n"
"process\n"
"text\n"
"L1:\n"
" write: x := 1;\n"
" read: y = 0;\n"
"CS:\n"
" write: x := 0;\n"
" goto L1\n"
"process\n"
"text\n"
"L1:\n"
" write: y := 1;\n"
" read: x = 0;\n"
"CS:\n"
" write: y := 0;\n"
" goto L1\n"
);
VipsBitReachability reach;
Arg arg(*m);
Result *res = reach.reachability(&arg);
Test::inner_test("#1 Simple Dekker",res->result == REACHABLE);
delete res;
delete m;
}
/* Test 2: Dekker 1 syncwr */
{
Machine *m = get_machine
("forbidden CS CS\n"
"data\n"
" x = 0 : [0:1]\n"
" y = 0 : [0:1]\n"
"process\n"
"text\n"
"L1:\n"
" syncwr: x := 1;\n"
" read: y = 0;\n"
"CS:\n"
" write: x := 0;\n"
" goto L1\n"
"process\n"
"text\n"
"L1:\n"
" write: y := 1;\n"
" read: x = 0;\n"
"CS:\n"
" write: y := 0;\n"
" goto L1\n"
);
VipsBitReachability reach;
Arg arg(*m);
Result *res = reach.reachability(&arg);
Test::inner_test("#2 Simple Dekker",res->result == REACHABLE);
delete res;
delete m;
}
/* Test 3: Dekker 1 syncwr (other process) */
{
Machine *m = get_machine
("forbidden CS CS\n"
"data\n"
" x = 0 : [0:1]\n"
" y = 0 : [0:1]\n"
"process\n"
"text\n"
"L1:\n"
" write: x := 1;\n"
" read: y = 0;\n"
"CS:\n"
" write: x := 0;\n"
" goto L1\n"
"process\n"
"text\n"
"L1:\n"
" syncwr: y := 1;\n"
" read: x = 0;\n"
"CS:\n"
" write: y := 0;\n"
" goto L1\n"
);
VipsBitReachability reach;
Arg arg(*m);
Result *res = reach.reachability(&arg);
Test::inner_test("#3 Simple Dekker",res->result == REACHABLE);
delete res;
delete m;
}
/* Test 4: Dekker syncwr in both processes */
{
Machine *m = get_machine
("forbidden CS CS\n"
"data\n"
" x = 0 : [0:1]\n"
" y = 0 : [0:1]\n"
"process\n"
"text\n"
"L1:\n"
" syncwr: x := 1;\n"
" read: y = 0;\n"
"CS:\n"
" write: x := 0;\n"
" goto L1\n"
"process\n"
"text\n"
"L1:\n"
" syncwr: y := 1;\n"
" read: x = 0;\n"
"CS:\n"
" write: y := 0;\n"
" goto L1\n"
);
VipsBitReachability reach;
Arg arg(*m);
Result *res = reach.reachability(&arg);
Test::inner_test("#4 Simple Dekker",res->result == REACHABLE);
delete res;
delete m;
}
/* Test 5: Dekker fence in one process */
{
Machine *m = get_machine
("forbidden CS CS\n"
"data\n"
" x = 0 : [0:1]\n"
" y = 0 : [0:1]\n"
"process\n"
"text\n"
"L1:\n"
" write: x := 1;\n"
" fence;\n"
" read: y = 0;\n"
"CS:\n"
" write: x := 0;\n"
" goto L1\n"
"process\n"
"text\n"
"L1:\n"
" write: y := 1;\n"
" read: x = 0;\n"
"CS:\n"
" write: y := 0;\n"
" goto L1\n"
);
VipsBitReachability reach;
Arg arg(*m);
Result *res = reach.reachability(&arg);
Test::inner_test("#5 Simple Dekker",res->result == REACHABLE);
delete res;
delete m;
}
/* Test 6: Dekker fence in one process */
{
Machine *m = get_machine
("forbidden CS CS\n"
"data\n"
" x = 0 : [0:1]\n"
" y = 0 : [0:1]\n"
"process\n"
"text\n"
"L1:\n"
" write: x := 1;\n"
" read: y = 0;\n"
"CS:\n"
" write: x := 0;\n"
" goto L1\n"
"process\n"
"text\n"
"L1:\n"
" write: y := 1;\n"
" fence;\n"
" read: x = 0;\n"
"CS:\n"
" write: y := 0;\n"
" goto L1\n"
);
VipsBitReachability reach;
Arg arg(*m);
Result *res = reach.reachability(&arg);
Test::inner_test("#6 Simple Dekker",res->result == REACHABLE);
delete res;
delete m;
}
/* Test 7: Dekker fence in both processes */
{
Machine *m = get_machine
("forbidden CS CS\n"
"data\n"
" x = 0 : [0:1]\n"
" y = 0 : [0:1]\n"
"process\n"
"text\n"
"L1:\n"
" write: x := 1;\n"
" fence;\n"
" read: y = 0;\n"
"CS:\n"
" write: x := 0;\n"
" goto L1\n"
"process\n"
"text\n"
"L1:\n"
" write: y := 1;\n"
" fence;\n"
" read: x = 0;\n"
"CS:\n"
" write: y := 0;\n"
" goto L1\n"
);
VipsBitReachability reach;
Arg arg(*m);
Result *res = reach.reachability(&arg);
Test::inner_test("#7 Simple Dekker",res->result == UNREACHABLE);
delete res;
delete m;
}
/* Test 8: IRIW */
{
Machine *m = get_machine
("forbidden * * END END\n"
"data\n"
" x = 0 : [0:1]\n"
" y = 0 : [0:1]\n"
"process\n"
"text\n"
" write: x := 1\n"
"process\n"
"text\n"
" write: y := 1\n"
"process\n"
"text\n"
" read: x = 1;\n"
" read: y = 0;\n"
" END: nop\n"
"process\n"
"text\n"
" read: y = 1;\n"
" read: x = 0;\n"
" END: nop\n"
);
VipsBitReachability reach;
Arg arg(*m);
Result *res = reach.reachability(&arg);
Test::inner_test("#8 IRIW (with R->R relaxation)",res->result == REACHABLE);
delete res;
delete m;
}
/* Test 9: IRIW */
{
Machine *m = get_machine
("forbidden * * END END\n"
"data\n"
" x = 0 : [0:1]\n"
" y = 0 : [0:1]\n"
"process\n"
"text\n"
" write: x := 1\n"
"process\n"
"text\n"
" write: y := 1\n"
"process\n"
"text\n"
" read: x = 1;\n"
" fence;\n"
" read: y = 0;\n"
" END: nop\n"
"process\n"
"text\n"
" read: y = 1;\n"
" fence;\n"
" read: x = 0;\n"
" END: nop\n"
);
VipsBitReachability reach;
Arg arg(*m);
Result *res = reach.reachability(&arg);
Test::inner_test("#9 IRIW (with R->R fence)",res->result == UNREACHABLE);
delete res;
delete m;
}
/* Test 10: IRIW */
{
Machine *m = get_machine
("forbidden * * END END\n"
"data\n"
" x = 0 : [0:1]\n"
" y = 0 : [0:1]\n"
"process\n"
"text\n"
" write: x := 1\n"
"process\n"
"text\n"
" write: y := 1\n"
"process\n"
"registers\n"
" $r0 = * : [0:1]\n"
"text\n"
" read: $r0 := x;\n"
" if $r0 = 1 then{\n"
" read: y = 0;\n"
" END: nop\n"
" }\n"
"process\n"
"registers\n"
" $r0 = * : [0:1]\n"
"text\n"
" read: $r0 := y;\n"
" if $r0 = 1 then{\n"
" read: x = 0;\n"
" END: nop\n"
" }\n"
);
VipsBitReachability reach;
Arg arg(*m);
Result *res = reach.reachability(&arg);
Test::inner_test("#10 IRIW (with R->R ctrl dependency)",res->result == REACHABLE);
delete res;
delete m;
}
/* Test 11: CAS-lock */
{
Machine *m = get_machine
("forbidden\n"
" BAD *\n"
"\n"
"data\n"
" l = 0 : [0:1]\n"
" x = 0 : [0:1]\n"
"\n"
"macro lock()\n"
" cas(l,0,1);\n"
" fence\n"
"endmacro\n"
"\n"
"macro unlock()\n"
" fence;\n"
" syncwr: l := 0\n"
"endmacro\n"
"\n"
"process\n"
"registers\n"
" $r0 = 0 : [0:1]\n"
"text\n"
" L0:\n"
" lock();\n"
" read: $r0 := x;\n"
" if $r0 = 1 then goto BAD;\n"
" unlock();\n"
" goto L0;\n"
"BAD: nop\n"
"\n"
"process\n"
"text\n"
"L0:\n"
" lock();\n"
" write: x := 1;\n"
" write: x := 0;\n"
" unlock();\n"
" goto L0\n"
);
VipsBitReachability reach;
Arg arg(*m);
Result *res = reach.reachability(&arg);
Test::inner_test("#11 CAS-lock (correct)",res->result == UNREACHABLE);
delete res;
delete m;
}
/* Test 12: CAS-lock */
{
Machine *m = get_machine
("forbidden\n"
" BAD *\n"
"\n"
"data\n"
" l = 0 : [0:1]\n"
" x = 0 : [0:1]\n"
"\n"
"macro lock()\n"
" cas(l,0,1);\n"
" fence\n"
"endmacro\n"
"\n"
"macro unlock()\n"
" syncwr: l := 0;\n" /* <- swapped order between syncwr and fence */
" fence\n"
"endmacro\n"
"\n"
"process\n"
"registers\n"
" $r0 = 0 : [0:1]\n"
"text\n"
" L0:\n"
" lock();\n"
" read: $r0 := x;\n"
" if $r0 = 1 then goto BAD;\n"
" unlock();\n"
" goto L0;\n"
"BAD: nop\n"
"\n"
"process\n"
"text\n"
"L0:\n"
" lock();\n"
" write: x := 1;\n"
" write: x := 0;\n"
" unlock();\n"
" goto L0\n"
);
VipsBitReachability reach;
Arg arg(*m);
Result *res = reach.reachability(&arg);
Test::inner_test("#12 CAS-lock (incorrect)",res->result == REACHABLE);
delete res;
delete m;
}
/* Test 13: Syncrd (dekker) */
{
Machine *m = get_machine(R"(
forbidden
CS CS
data
x = 0 : [0:1]
y = 0 : [0:1]
process
text
syncwr: x := 1;
syncrd: y = 0;
CS: nop
process
text
syncwr: y := 1;
syncrd: x = 0;
CS: nop
)");
VipsBitReachability reach;
Arg arg(*m);
Result *res = reach.reachability(&arg);
Test::inner_test("#13 Syncrd",res->result == UNREACHABLE);
delete res;
delete m;
}
/* Test 14: Syncrd (dekker variation) */
{
Machine *m = get_machine(R"(
forbidden
CS CS
data
x = 0 : [0:1]
y = 0 : [0:1]
process
text
syncwr: x := 1;
syncrd: y = 1;
CS: nop
process
text
syncwr: y := 1;
syncrd: x = 0;
CS: nop
)");
VipsBitReachability reach;
Arg arg(*m);
Result *res = reach.reachability(&arg);
Test::inner_test("#14 Syncrd",res->result == REACHABLE);
delete res;
delete m;
}
/* Test 15: Syncrd (dekker) */
{
Machine *m = get_machine(R"(
forbidden
CS CS
data
x = 0 : [0:1]
y = 0 : [0:1]
process
registers
$r0 = 0 : [0:1]
text
syncwr: x := 1;
syncrd: $r0 := y;
assume: $r0 = 0;
CS: nop
process
registers
$r0 = 0 : [0:1]
text
syncwr: y := 1;
syncrd: $r0 := x;
assume: $r0 = 0;
CS: nop
)");
VipsBitReachability reach;
Arg arg(*m);
Result *res = reach.reachability(&arg);
Test::inner_test("#15 Syncrd",res->result == UNREACHABLE);
delete res;
delete m;
}
/* Test 16: Syncrd (dekker variation) */
{
Machine *m = get_machine(R"(
forbidden
CS CS
data
x = 0 : [0:1]
y = 0 : [0:1]
process
registers
$r0 = 0 : [0:1]
text
syncwr: x := 1;
syncrd: $r0 := y;
assume: $r0 = 0;
CS: nop
process
registers
$r0 = 0 : [0:1]
text
syncwr: y := 1;
syncrd: $r0 := x;
assume: $r0 = 1;
CS: nop
)");
VipsBitReachability reach;
Arg arg(*m);
Result *res = reach.reachability(&arg);
Test::inner_test("#16 Syncrd",res->result == REACHABLE);
delete res;
delete m;
}
/* Test 17: Syncrd (dekker) */
{
Machine *m = get_machine(R"(
forbidden
CS CS
data
x = 0 : [0:1]
y = 0 : [0:1]
process
text
write: x := 1;
syncrd: x = 1;
syncrd: y = 0;
CS: nop
process
text
write: y := 1;
syncrd: y = 1;
syncrd: x = 0;
CS: nop
)");
VipsBitReachability reach;
Arg arg(*m);
Result *res = reach.reachability(&arg);
Test::inner_test("#17 Syncrd (rowe)",res->result == REACHABLE);
delete res;
delete m;
}
/* Test 18: Syncrd (dekker) */
{
Machine *m = get_machine(R"(
forbidden
CS CS
data
x = 0 : [0:1]
y = 0 : [0:1]
process
registers
$r0 = 0 : [0:1]
text
write: x := 1;
syncrd: $r0 := x;
syncrd: y = 0;
CS: nop
process
registers
$r0 = 0 : [0:1]
text
write: y := 1;
syncrd: $r0 := y;
syncrd: x = 0;
CS: nop
)");
VipsBitReachability reach;
Arg arg(*m);
Result *res = reach.reachability(&arg);
Test::inner_test("#18 Syncrd (rowe)",res->result == REACHABLE);
delete res;
delete m;
}
/* Test 19: Syncrd (dekker) */
{
Machine *m = get_machine(R"(
forbidden
CS CS
data
x = 0 : [0:1]
y = 0 : [0:1]
process
text
write: x := 1;
syncrd: x = 0;
syncrd: y = 0;
CS: nop
process
text
write: y := 1;
syncrd: y = 1;
syncrd: x = 0;
CS: nop
)");
VipsBitReachability reach;
Arg arg(*m);
Result *res = reach.reachability(&arg);
Test::inner_test("#19 Syncrd (rowe)",res->result == UNREACHABLE);
delete res;
delete m;
}
/* Test 20: Syncrd (dekker) */
{
Machine *m = get_machine(R"(
forbidden
L0 CS CS
data
x = 0 : [0:1]
y = 0 : [0:1]
z = 0 : [0:1]
process
text
L0: write: z := 0;
goto L0
process
text
write: x := 1;
write: z := 1;
syncrd: z = 0;
syncrd: y = 0;
CS: nop
process
text
write: y := 1;
write: z := 1;
syncrd: z = 0;
syncrd: x = 0;
CS: nop
)");
VipsBitReachability reach;
Arg arg(*m);
Result *res = reach.reachability(&arg);
Test::inner_test("#20 Syncrd (rowe)",res->result == REACHABLE);
delete res;
delete m;
}
/* Test 21: Syncrd (dekker) */
{
Machine *m = get_machine(R"(
forbidden
L0 CS CS
data
x = 0 : [0:1]
y = 0 : [0:1]
z = 0 : [0:1]
process
text
L0: write: z := 0;
goto L0
process
text
write: x := 1;
write: z := 1;
syncrd: z = 1;
syncrd: y = 0;
CS: nop
process
text
write: y := 1;
write: z := 1;
syncrd: z = 0;
syncrd: x = 0;
CS: nop
)");
VipsBitReachability reach;
Arg arg(*m);
Result *res = reach.reachability(&arg);
Test::inner_test("#21 Syncrd (rowe)",res->result == REACHABLE);
delete res;
delete m;
}
/* Test 22: Syncrd (coherence) */
{
Machine *m = get_machine(R"(
forbidden
END END
data
x = 0 : [0:1]
process
text
write: x := 1;
END: nop
process
text
syncrd: x = 1;
read: x = 0;
END: nop
)");
VipsBitReachability reach;
Arg arg(*m);
Result *res = reach.reachability(&arg);
Test::inner_test("#22 Syncrd (coherence)",res->result == UNREACHABLE);
delete res;
delete m;
}
/* Test 23: Syncrd (coherence) */
{
Machine *m = get_machine(R"(
forbidden
END END
data
x = 0 : [0:1]
process
text
write: x := 1;
END: nop
process
text
syncrd: x = 1;
syncrd: x = 0;
END: nop
)");
VipsBitReachability reach;
Arg arg(*m);
Result *res = reach.reachability(&arg);
Test::inner_test("#23 Syncrd (coherence)",res->result == UNREACHABLE);
delete res;
delete m;
}
/* Test 24: Syncrd (coherence) */
{
Machine *m = get_machine(R"(
forbidden
END END
data
x = 0 : [0:1]
process
text
write: x := 1;
END: nop
process
registers
$r0 = 0 : [0:1]
text
syncrd: $r0 := x;
assume: $r0 = 1;
read: x = 0;
END: nop
)");
VipsBitReachability reach;
Arg arg(*m);
Result *res = reach.reachability(&arg);
Test::inner_test("#24 Syncrd (coherence)",res->result == UNREACHABLE);
delete res;
delete m;
}
/* Test 25: Syncrd (coherence) */
{
Machine *m = get_machine(R"(
forbidden
END END
data
x = 0 : [0:1]
process
text
write: x := 1;
END: nop
process
registers
$r0 = 0 : [0:1]
text
syncrd: $r0 := x;
assume: $r0 = 1;
syncrd: x = 0;
END: nop
)");
VipsBitReachability reach;
Arg arg(*m);
Result *res = reach.reachability(&arg);
Test::inner_test("#25 Syncrd (coherence)",res->result == UNREACHABLE);
delete res;
delete m;
}
};
int main (int argc, char *argv[])
{
int n, ib = 0, nb, flags = 0, has_q = 0;
BINARYIO *bf;
static char basename[33] = "Base";
if (argc < 3)
print_usage (usgmsg, NULL);
/* get options */
while ((n = getargs (argc, argv, options)) > 0) {
switch (n) {
case 'f':
flags &= ~OPEN_FORTRAN;
flags |= OPEN_ASCII;
break;
case 'u':
flags &= ~OPEN_ASCII;
flags |= OPEN_FORTRAN;
break;
case 's':
mblock = 0;
break;
case 'p':
whole = 0;
break;
case 'i':
use_iblank = 1;
/* fall through */
case 'n':
has_iblank = 1;
break;
case 'd':
is_double = 1;
break;
case 'M':
flags &= ~MACH_UNKNOWN;
flags |= get_machine (argarg);
break;
case 'b':
ib = atoi (argarg);
break;
case 'B':
strncpy (basename, argarg, 32);
basename[32] = 0;
break;
case 'g':
gamma = atof (argarg);
if (gamma <= 1.0)
FATAL (NULL, "invalid value for gamma");
break;
case 'c':
convert = 1;
break;
}
}
if (argind > argc - 2)
print_usage (usgmsg, "XYZfile and/or CGNSfile not given");
/* read Plot3d file */
printf ("reading PLOT3D grid file %s\n", argv[argind]);
printf (" as %s-block %s", mblock ? "multi" : "single",
flags == OPEN_ASCII ? "ASCII" :
(flags == OPEN_FORTRAN ? "FORTRAN unformatted" : "binary"));
if (has_iblank) printf (" with iblank array");
putchar ('\n');
if (!file_exists (argv[argind]))
FATAL (NULL, "XYZ file does not exist or is not a file");
if (NULL == (bf = bf_open (argv[argind], flags | OPEN_READ))) {
fprintf (stderr, "can't open <%s> for reading", argv[argind]);
exit (1);
}
read_xyz (bf);
bf_close (bf);
if (use_iblank) build_interfaces ();
/* read solution file if given */
if (++argind < argc-1) {
printf ("\nreading PLOT3D solution file %s\n", argv[argind]);
if (!file_exists (argv[argind]))
FATAL (NULL, "Solution file does not exist or is not a file");
if (NULL == (bf = bf_open (argv[argind], flags | OPEN_READ))) {
fprintf (stderr, "can't open <%s> for reading", argv[argind]);
exit (1);
}
read_q (bf);
bf_close (bf);
argind++;
has_q = 1;
}
/* open CGNS file */
printf ("\nwriting CGNS file to %s\n", argv[argind]);
nb = open_cgns (argv[argind], 0);
if (ib) {
if (ib > nb)
FATAL (NULL, "specified base index out of range");
if (cg_base_read (cgnsfn, ib, basename, &n, &n))
FATAL (NULL, NULL);
}
if (cg_base_write (cgnsfn, basename, 3, 3, &cgnsbase) ||
cg_goto (cgnsfn, cgnsbase, "end") ||
cg_dataclass_write (CGNS_ENUMV(NormalizedByUnknownDimensional)))
FATAL (NULL, NULL);
printf (" output to base %d - %s\n", cgnsbase, basename);
write_zones ();
for (n = 1; n <= nZones; n++) {
printf ("writing zone %d ... grid", n);
fflush (stdout);
write_zone_grid (n);
write_zone_interface (n);
if (has_q) {
printf (", solution");
fflush (stdout);
write_zone_solution (n, 1);
write_solution_field (n, 1, 0);
}
puts (" done");
}
if (has_q) write_reference ();
cg_close (cgnsfn);
return 0;
}
