void variant_memory_init_params(MEMORY_INIT_UPD *memory_params)
{
int ram_id = get_ramid();
/*
* RAMID = 5 - 4GiB Micron MT52L256M32D1PF-107
* RAMID = 7 - 2GiB Micron MT52L256M32D1PF-107
*/
if (ram_id == 5 || ram_id == 7) {
/*
* For new micron part, it requires read/receive
* enable training before sending cmds to get MR8.
* To override dram geometry settings as below:
*
* PcdDramWidth = x32
* PcdDramDensity = 8Gb
* PcdDualRankDram = disable
*/
memory_params->PcdRxOdtLimitChannel0 = 1;
memory_params->PcdRxOdtLimitChannel1 = 1;
memory_params->PcdDisableAutoDetectDram = 1;
memory_params->PcdDramWidth = 2;
memory_params->PcdDramDensity = 3;
memory_params->PcdDualRankDram = 0;
}
}
static void *get_spd_pointer(char *spd_file_content, int total_spds, int *dual)
{
int ram_id = 0;
int spd_index = 0;
ram_id = get_ramid();
printk(BIOS_DEBUG, "ram_id=%d, total_spds: %d\n", ram_id, total_spds);
spd_index = get_variant_spd_index(ram_id, dual);
if (spd_index >= total_spds) {
printk(BIOS_ERR, "SPD index > total SPDs\n");
return NULL;
}
/* Return the serial product data for the RAM */
return &spd_file_content[SPD_PAGE_LEN * spd_index];
}
