/*
* SB600 VFSMAF (VID/FID System Management Action Field) is 010b by default.
* RPR 2.3.3 C-state and VID/FID change for the K8 platform.
*/
static void enable_fid_change_on_sb(u32 sbbusn, u32 sbdn)
{
u8 byte;
byte = pmio_read(0x9a);
byte &= ~0x34;
if (dual_core())
byte |= 0x34;
else
byte |= 0x04;
pmio_write(0x9a, byte);
byte = pmio_read(0x8f);
byte &= ~0x30;
byte |= 0x20;
pmio_write(0x8f, byte);
pmio_write(0x8b, 0x01);
pmio_write(0x8a, 0x90);
if(get_sb600_revision() > 0x13)
pmio_write(0x88, 0x10);
else
pmio_write(0x88, 0x06);
byte = pmio_read(0x7c);
byte &= ~0x01;
byte |= 0x01;
pmio_write(0x7c, byte);
/* Must be 0 for K8 platform. */
byte = pmio_read(0x68);
byte &= ~0x01;
pmio_write(0x68, byte);
/* Must be 0 for K8 platform. */
byte = pmio_read(0x8d);
byte &= ~(1<<6);
pmio_write(0x8d, byte);
byte = pmio_read(0x61);
byte &= ~0x04;
pmio_write(0x61, byte);
byte = pmio_read(0x42);
byte &= ~0x04;
pmio_write(0x42, byte);
if (get_sb600_revision() == 0x14) {
pmio_write(0x89, 0x10);
byte = pmio_read(0x52);
byte |= 0x80;
pmio_write(0x52, byte);
}
}
/*
SB600 VFSMAF (VID/FID System Management Action Field) is 010b by default.
RPR 2.3.3 C-state and VID/FID change for the K8 platform.
*/
void enable_fid_change_on_sb(u32 sbbusn, u32 sbdn)
{
u8 byte;
byte = pm_ioread(0x9a);
byte &= ~0x34;
byte |= 0x04; // single core
pm_iowrite(0x9a, byte);
byte = pm_ioread(0x8f);
byte &= ~0x30;
byte |= 0x20;
pm_iowrite(0x8f, byte);
pm_iowrite(0x8b, 0x01);
pm_iowrite(0x8a, 0x90);
if(get_sb600_revision() > REV_SB600_A13)
pm_iowrite(0x88, 0x10);
else
pm_iowrite(0x88, 0x06);
byte = pm_ioread(0x7c);
byte &= ~0x01;
byte |= 0x01;
pm_iowrite(0x7c, byte);
/*Must be 0 for K8 platform.*/
byte = pm_ioread(0x68);
byte &= ~0x01;
pm_iowrite(0x68, byte);
/*Must be 0 for K8 platform.*/
byte = pm_ioread(0x8d);
byte &= ~(1<<6);
pm_iowrite(0x8d, byte);
byte = pm_ioread(0x61);
byte &= ~0x04;
pm_iowrite(0x61, byte);
byte = pm_ioread(0x42);
byte &= ~0x04;
pm_iowrite(0x42, byte);
if(get_sb600_revision() == REV_SB600_A21) {
pm_iowrite(0x89, 0x10);
byte = pm_ioread(0x52);
byte |= 0x80;
pm_iowrite(0x52, byte);
}
}
/*
* sb_hpet_cfg :
* config the HPET module
*/
void sb_hpet_cfg(void)
{
u8 rev = get_sb600_revision();
pcitag_t sm_dev = _pci_make_tag(0, 20, 0);
PRINTF_DEBUG();
#ifdef CFG_ATI_HPET_BASE
#if CFG_ATI_HPET_BASE
if(ati_sb_cfg.hpet_en == SB_ENABLE){
if(rev >= REV_SB600_A21){
set_pm_enable_bits(0x55, 1 << 7, 0 << 7);
}
ati_sb_cfg.hpet_base = CFG_ATI_HPET_BASE;
_pci_conf_write(sm_dev, 0x14, ati_sb_cfg.hpet_base);
set_sbcfg_enable_bits(sm_dev, 0x64, 1 << 10, 1 << 10);
}
#endif
#endif
if(rev >= REV_SB600_A21){
set_pm_enable_bits(0x55, 1 << 7, 1 << 7);
set_pm_enable_bits(0x52, 1 << 6, 1 << 6);
}
return;
}
void sb_last_init(void)
{
pcitag_t sm_dev;
u16 sm_id;
DEBUG_INFO("\n+++++++++++++++++SB LAST STAGE : start with type(0x%x), revision(0x%x)++++++++++++++++++++++++++\n",
get_sb600_platform(), get_sb600_revision());
/* judge the device : liujl ??? */
sm_dev = _pci_make_tag(0, 20, 0);
sm_id = _pci_conf_readn(sm_dev, 0x02, 2);
if(sm_id != SB600_DEVICE_ID){
if(sm_id != 0x43C5){
DEBUG_INFO("SB LAST STAGE : out with ID mismatch (0x%x) match(0x%x)\n", sm_id, SB600_DEVICE_ID);
//while(1);
}
}
DEBUG_INFO("SB LAST STAGE : ID judge 0x%x\n", sm_id);
sb_last_post_setting();
sb_last_c3_popup_setting();
sb_last_c3_popup_next_setting();
sb_last_p4_init();
sb_last_am97_init();
sb_last_sata_unconnected_shutdown_clock();
sb_last_cmos_init();
// sb_last_sata_cache();
// sb_last_sata_init();
sb_last_init_pci_autoclock_run();
sb_last_smi_service_check();
DEBUG_INFO("---------------------------------- SB LAST STAGE DONE---------------------------------------\n");
return;
}
void sb_last_post_setting(void)
{
u8 rev = get_sb600_revision();
pcitag_t pcib_dev;
PRINTF_DEBUG();
if(rev == REV_SB600_A11){
update_hpet_table();
}
if(rev == REV_SB600_A12){
/* clear HPET ECC */
set_pm_enable_bits(0x9A, 1 << 7, 0 << 7);
}
if(rev >= REV_SB600_A13){
/* clear HPET ECC */
set_pm_enable_bits(0x9A, 1 << 7, 0 << 7);
/* enable load new value for HPET */
set_pm_enable_bits(0x9F, 1 << 5, 1 << 5);
/* make HPET revision id to be 0x01 */
set_pm_enable_bits(0x9E, (1 << 6) | (1 << 7), (1 << 6) | (1 << 7));
}
if(ati_sb_cfg.hpet_en == SB_DISABLE){
update_hpet_table();
}
/* RPR4.5 Master Latency Timer PCIB_PCI_config 0x0D/0x1B = 0x40
* Enables the PCIB to retain ownership of the bus on the
* Primary side and on the Secondary side when GNT# is deasserted.
*/
pcib_dev = _pci_make_tag(0, 20, 4);
_pci_conf_writen(pcib_dev, 0x0D, 0x40, 1);
_pci_conf_writen(pcib_dev, 0x1B, 0x40, 1);
return;
}
/*
* Compliant with CIM_48's sbPciCfg.
* Add any south bridge setting.
*/
static void sb600_pci_cfg(void)
{
device_t dev;
u8 byte;
/* SMBus Device, BDF:0-20-0 */
dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0);
/* Enable the hidden revision ID, available after A13. */
byte = pci_read_config8(dev, 0x70);
byte |= (1 << 8);
pci_write_config8(dev, 0x70, byte);
/* rpr2.20 Disable Timer IRQ Enhancement for proper operation of the 8254 timer, 0xae[5]. */
byte = pci_read_config8(dev, 0xae);
byte |= (1 << 5);
pci_write_config8(dev, 0xae, byte);
/* Enable watchdog decode timer */
byte = pci_read_config8(dev, 0x41);
byte |= (1 << 3);
pci_write_config8(dev, 0x41, byte);
/* Set to 1 to reset USB on the software (such as IO-64 or IO-CF9 cycles)
* generated PCIRST#. */
byte = pmio_read(0x65);
byte |= (1 << 4);
pmio_write(0x65, byte);
/*For A13 and above. */
if (get_sb600_revision() > 0x12) {
/* rpr2.16 C-State Reset, PMIO 0x9f[7]. */
byte = pmio_read(0x9f);
byte |= (1 << 7);
pmio_write(0x9f, byte);
/* rpr2.17 PCI Clock Period will increase to 30.8ns. 0x53[7]. */
byte = pmio_read(0x53);
byte |= (1 << 7);
pmio_write(0x53, byte);
}
/* IDE Device, BDF:0-20-1 */
dev = pci_locate_device(PCI_ID(0x1002, 0x438C), 0);
/* Enable IDE Explicit prefetch, 0x63[0] clear */
byte = pci_read_config8(dev, 0x63);
byte &= 0xfe;
pci_write_config8(dev, 0x63, byte);
/* LPC Device, BDF:0-20-3 */
dev = pci_locate_device(PCI_ID(0x1002, 0x438D), 0);
/* rpr7.2 Enabling LPC DMA function. */
byte = pci_read_config8(dev, 0x40);
byte |= (1 << 2);
pci_write_config8(dev, 0x40, byte);
/* rpr7.3 Disabling LPC TimeOut. 0x48[7] clear. */
byte = pci_read_config8(dev, 0x48);
byte &= 0x7f;
pci_write_config8(dev, 0x48, byte);
/* rpr7.5 Disabling LPC MSI Capability, 0x78[1] clear. */
byte = pci_read_config8(dev, 0x78);
byte &= 0xfd;
pci_write_config8(dev, 0x78, byte);
/* SATA Device, BDF:0-18-0, Non-Raid-5 SATA controller */
dev = pci_locate_device(PCI_ID(0x1002, 0x4380), 0);
/* rpr6.8 Disabling SATA MSI Capability, for A13 and above, 0x42[7]. */
if (0x12 < get_sb600_revision()) {
u32 reg32;
reg32 = pci_read_config32(dev, 0x40);
reg32 |= (1 << 23);
pci_write_config32(dev, 0x40, reg32);
}
/* EHCI Device, BDF:0-19-5, ehci usb controller */
dev = pci_locate_device(PCI_ID(0x1002, 0x4386), 0);
/* rpr5.10 Disabling USB EHCI MSI Capability. 0x50[6]. */
byte = pci_read_config8(dev, 0x50);
byte |= (1 << 6);
pci_write_config8(dev, 0x50, byte);
/* OHCI0 Device, BDF:0-19-0, ohci usb controller #0 */
dev = pci_locate_device(PCI_ID(0x1002, 0x4387), 0);
/* rpr5.11 Disabling USB OHCI MSI Capability. 0x40[12:8]=0x1f. */
byte = pci_read_config8(dev, 0x41);
byte |= 0x1f;
pci_write_config8(dev, 0x41, byte);
}
/* sbDevicesPorInitTable */
static void sb600_devices_por_init(void)
{
device_t dev;
u8 byte;
printk(BIOS_INFO, "sb600_devices_por_init()\n");
/* SMBus Device, BDF:0-20-0 */
printk(BIOS_INFO, "sb600_devices_por_init(): SMBus Device, BDF:0-20-0\n");
dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0);
if (dev == PCI_DEV_INVALID) {
die("SMBUS controller not found\n");
/* NOT REACHED */
}
printk(BIOS_INFO, "SMBus controller enabled, sb revision is 0x%x\n",
get_sb600_revision());
/* sbPorAtStartOfTblCfg */
/* Set A-Link bridge access address. This address is set at device 14h, function 0, register 0xf0.
* This is an I/O address. The I/O address must be on 16-byte boundary. */
pci_write_config32(dev, 0xf0, AB_INDX);
/* To enable AB/BIF DMA access, a specific register inside the BIF register space needs to be configured first. */
/*Enables the SB600 to send transactions upstream over A-Link Express interface. */
axcfg_reg(0x04, 1 << 2, 1 << 2);
axindxc_reg(0x21, 0xff, 0);
/* 2.3.5:Enabling Non-Posted Memory Write for the K8 Platform */
axindxc_reg(0x10, 1 << 9, 1 << 9);
/* END of sbPorAtStartOfTblCfg */
/* sbDevicesPorInitTables */
/* set smbus iobase */
pci_write_config32(dev, 0x10, SMBUS_IO_BASE | 1);
/* enable smbus controller interface */
byte = pci_read_config8(dev, 0xd2);
byte |= (1 << 0);
pci_write_config8(dev, 0xd2, byte);
/* set smbus 1, ASF 2.0 (Alert Standard Format), iobase */
pci_write_config16(dev, 0x58, SMBUS_IO_BASE | 0x11);
/* TODO: I don't know the usage of followed two lines. I copied them from CIM. */
pci_write_config8(dev, 0x0a, 0x1);
pci_write_config8(dev, 0x0b, 0x6);
/* KB2RstEnable */
pci_write_config8(dev, 0x40, 0xd4);
/* Enable ISA Address 0-960K decoding */
pci_write_config8(dev, 0x48, 0x0f);
/* Enable ISA Address 0xC0000-0xDFFFF decode */
pci_write_config8(dev, 0x49, 0xff);
/* Enable decode cycles to IO C50, C51, C52 GPM controls. */
byte = pci_read_config8(dev, 0x41);
byte &= 0x80;
byte |= 0x33;
pci_write_config8(dev, 0x41, byte);
/* Legacy DMA Prefetch Enhancement, CIM masked it. */
/* pci_write_config8(dev, 0x43, 0x1); */
/* Disabling Legacy USB Fast SMI# */
byte = pci_read_config8(dev, 0x62);
byte |= 0x24;
pci_write_config8(dev, 0x62, byte);
/* Features Enable */
pci_write_config32(dev, 0x64, 0x829E7DBF); /* bit10: Enables the HPET interrupt. */
/* SerialIrq Control */
pci_write_config8(dev, 0x69, 0x90);
/* Test Mode, PCIB_SReset_En Mask is set. */
pci_write_config8(dev, 0x6c, 0x20);
/* IO Address Enable, CIM set 0x78 only and masked 0x79. */
/*pci_write_config8(dev, 0x79, 0x4F); */
pci_write_config8(dev, 0x78, 0xFF);
/* This register is not used on sb600. It came from older chipset. */
/*pci_write_config8(dev, 0x95, 0xFF); */
/* Set smbus iospace enable, I don't know why write 0x04 into reg5 that is reserved */
pci_write_config16(dev, 0x4, 0x0407);
/* clear any lingering errors, so the transaction will run */
outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
/* IDE Device, BDF:0-20-1 */
printk(BIOS_INFO, "sb600_devices_por_init(): IDE Device, BDF:0-20-1\n");
dev = pci_locate_device(PCI_ID(0x1002, 0x438C), 0);
/* Disable prefetch */
byte = pci_read_config8(dev, 0x63);
byte |= 0x1;
pci_write_config8(dev, 0x63, byte);
/* LPC Device, BDF:0-20-3 */
printk(BIOS_INFO, "sb600_devices_por_init(): LPC Device, BDF:0-20-3\n");
dev = pci_locate_device(PCI_ID(0x1002, 0x438D), 0);
/* DMA enable */
pci_write_config8(dev, 0x40, 0x04);
/* LPC Sync Timeout */
pci_write_config8(dev, 0x49, 0xFF);
/* Enable Tpm12_en and Tpm_legacy. I don't know what is its usage and copied from CIM. */
pci_write_config8(dev, 0x7C, 0x05);
/* P2P Bridge, BDF:0-20-4, the configuration of the registers in this dev are copied from CIM,
* TODO: I don't know what are their mean? */
printk(BIOS_INFO, "sb600_devices_por_init(): P2P Bridge, BDF:0-20-4\n");
dev = pci_locate_device(PCI_ID(0x1002, 0x4384), 0);
/* I don't know why CIM tried to write into a read-only reg! */
/*pci_write_config8(dev, 0x0c, 0x20) */ ;
/* Arbiter enable. */
pci_write_config8(dev, 0x43, 0xff);
/* Set PCDMA request into height priority list. */
/* pci_write_config8(dev, 0x49, 0x1) */ ;
pci_write_config8(dev, 0x40, 0x26);
/* I don't know why CIM set reg0x1c as 0x11.
* System will block at sdram_initialize() if I set it before call sdram_initialize().
* If it is necessary to set reg0x1c as 0x11, please call this function after sdram_initialize().
* pci_write_config8(dev, 0x1c, 0x11);
* pci_write_config8(dev, 0x1d, 0x11);*/
/*CIM set this register; but I didn't find its description in RPR.
On DBM690T platform, I didn't find different between set and skip this register.
But on Filbert platform, the DEBUG message from serial port on Peanut board can't be displayed
after the bit0 of this register is set.
pci_write_config8(dev, 0x04, 0x21);
*/
pci_write_config8(dev, 0x0d, 0x40);
pci_write_config8(dev, 0x1b, 0x40);
/* Enable PCIB_DUAL_EN_UP will fix potential problem with PCI cards. */
pci_write_config8(dev, 0x50, 0x01);
/* SATA Device, BDF:0-18-0, Non-Raid-5 SATA controller */
printk(BIOS_INFO, "sb600_devices_por_init(): SATA Device, BDF:0-18-0\n");
dev = pci_locate_device(PCI_ID(0x1002, 0x4380), 0);
/*PHY Global Control, we are using A14.
* default: 0x2c40 for ASIC revision A12 and below
* 0x2c00 for ASIC revision A13 and above.*/
pci_write_config16(dev, 0x86, 0x2C00);
/* PHY Port0-3 Control */
pci_write_config32(dev, 0x88, 0xB400DA);
pci_write_config32(dev, 0x8c, 0xB400DA);
pci_write_config32(dev, 0x90, 0xB400DA);
pci_write_config32(dev, 0x94, 0xB400DA);
/* Port0-3 BIST Control/Status */
pci_write_config8(dev, 0xa5, 0xB8);
pci_write_config8(dev, 0xad, 0xB8);
pci_write_config8(dev, 0xb5, 0xB8);
pci_write_config8(dev, 0xbd, 0xB8);
}
void sb_last_c3_popup_next_setting(void)
{
u8 rev = get_sb600_revision();
u8 type = get_sb600_platform();
PRINTF_DEBUG();
if(type == K8_ID){
/* RPR2.3.3 C-State and VID/FID Change for the K8 Platform
* BIOS should not report BM_STS or ARB_DIS to OS if C3 pop-up is enabled.
* With C3 pop-up, ARB_DIS should not be set in any case and BM_STS
* is always cleared so OS will always issue C3.
*/
/* assume single core cpu is present */
set_pm_enable_bits(0x9A, ((1 << 2) | (1 << 4) | (1 << 5)), 1 << 2);
/* PM_IO 0x8F [4] = 0 for system with RS690
* Note: RS690 north bridge has AllowLdtStop built for both display and PCIE traffic to
* wake up the HT link. BmReq# needs to be ignored otherwise may cause LDTSTP# not
* to toggle.
*/
/* assume RS690 chipset is present */
set_pm_enable_bits(0x8F, (1 << 4) | (1 << 5), (1 << 5));
/* StutterTime=01 for minimum LDTSTP# assertion duration of 1us in C3 */
set_pm_enable_bits(0x8B, 0xFF, 0x01);
/* Enable stutter mode for C3 and set 2us duration for LDTSTP# assertion during
* VID/FID change
*/
set_pm_enable_bits(0x8A, 0xFF, 0x90);
/* Minimum LDTSTP# deassertion duration(in micro seconds) in stutter mode */
if(rev <= REV_SB600_A13){
set_pm_enable_bits(0x88, 0xFF, 0x06);
}else{
set_pm_enable_bits(0x88, 0xFF, 0x10);
}
/* Set to 1 to allow wakeup from C3 if break event happens before LDTSTOP# assertion */
set_pm_enable_bits(0x7C, 1 << 0, 1 << 0);
/* Must be 0 for k8 platforms as per RPR */
set_pm_enable_bits(0x68, 1 << 1, 0 << 1);
set_pm_enable_bits(0x8D, 1 << 6, 0 << 6);
/* This bit should be cleared if C3 popup is enabled. No sideeffect even if it
* is cleared otherwise
*/
set_pm_enable_bits(0x61, 1 << 2, 0 << 2);
/* Setting this bit will convert C2 into C3. We should clear this bit for usb to
* function properly.
*/
set_pm_enable_bits(0x42, 1 << 2, 0 << 2);
if(rev == REV_SB600_A21){
/* This setting provides 16us delay before the assertion of LDTSTOP# when C3
* is entered. The delay will allow USB DMA to go on in a continous manner
*/
set_pm_enable_bits(0x89, 0xff, 0x10);
/* Set this bit to allow pop-up request being latched during the minimum
* LDTSTP# assertion time
*/
set_pm_enable_bits(0x52, 0x00, 1 << 7);
}
}else{
/* RPR2.4.2 C-State Function for the P4 platform : Intel cpu C3 setting
* PM_IO 0x67 [2] = 1 For a P4 CPU that supports C-states deeper than C1,
* this bit must be set to enable the SB600 C-state function.
* PM_IO 0x67 [1] = 1 For a P4 CPU that supports the C3 function,
* this bit must be set to enable the SLP# function.
* PM_IO 0x68 [0] = 1 For a P4 CPU that supports the PBE# function,
* this bit must be set to 1 for the C-state to work properly.
* PM_IO 0x68 [1] = 0 With this bit set to 1, pending break event will prevent SB
* from entering C state. LVL read will be completed with no effect.
* The function will need to be qualified in the future. Currently this bit must be 0.
* PM_IO 0x8D [6] = 1 Right after SB exits from C state, LVL read will have no
* effect until the previous break event has been cleared. Setting the bit will
* prevent SB from sending STPCLK# message to NB during such time.
* This bit must be set to 1.
* PM_IO 0x71 [1] = 1 This bit enables pop-up in C3/4 state. For the internal
* bus mastering request, SB will deassert appropriate control signals and
* put CPU into C2 state. In the meanwhile NB will enable its arbiter.
* Then DMA can go through. When DMA finishes, SB will assert those signals
* again and put CPU back into C3/4 after some idle time.
* PM_IO 0x73 [7:0] = 80h (default) This register defines the idle time for C3/4 pop-up.
* The value corresponds to Alink clocks. With the default value "80" the
* delay is about 2us.
* PM_IO 0x72 [7:0] = 0Bh This register defines the delay between the deassertion
* of DPRSLPVR and CPU_STP# in C4 timing sequence.
* With the value "0B" the delay is 20 to 22 us.
* PM_IO 0x51 [5:0] = 05h This register defines the delay between the deassertion
* of CPU_STP# and SLP# in C3/4 timing sequence. With the value "05" the
* delay is 32 to 40 us.
* PM_IO 0x9A [5] = 1 For system with dual core CPU, set this bit to 1 to
* automatically clear BM_STS when the C3/4 sequence is being initiated..
* PM_IO 0x9A [4] = 1 Set this bit to 1 and BM_STS will cause C3 to pop-up or
* wakeup even if BM_RLD is not set to 1.
* PM_IO 0x9A [3] = 1 Set this bit to 1 to automatically disable the internal
* arbiter when C3/4 sequence is being started. The internal arbiter will be
* enabled again during pop-up or after wakeup.
* Smbus_PCI_config 0x64 [5] = 0 BmReq# is no longer used in P4 platform.
* Clear this bit to disable the BmReq# input.
* Smbus_PCI_config 0x64 [4] = 1
* PM_IO 0x61 [2] = 1 Set these two bits to enable the internal bus mastering
* to cause C3 pop-up.
* SB600 A13 and above PM_IO 0x51 [7] = 1 Set this bit to 1 to extend STPCLK#
* hold time with respect to SLP# to be more than 3us.
*/
set_pm_enable_bits(0x67, (1 << 1) | (1 << 2), (1 << 1) | (1 << 2));
set_pm_enable_bits(0x71, 1 << 1, 1 << 1);
set_pm_enable_bits(0x68, (1 << 0) | (1 << 1), 1 << 0);
set_pm_enable_bits(0x8D, 1 << 6, 1 << 6);
set_pm_enable_bits(0x73, 0xFF, 0x80);
set_pm_enable_bits(0x72, 0xFF, 0x0B);
set_pm_enable_bits(0x51, 0x3F, 0x05);
set_pm_enable_bits(0x9A, (1 << 3) | (1 << 4) | (1 << 5), (1 << 3) | (1 << 4) | (1 << 5));
set_pm_enable_bits(0x61, 1 << 2, 1 << 2);
if(rev > REV_SB600_A12){
set_pm_enable_bits(0x51, 1 << 7, 1 << 7);
}
/* Note: For SB600 to be paired with NB's that do not support C3/4 pop-up
* (rs690 SUPPORT this feature) following register settings should be followed :
* PM_IO 0x9A[5] = 0
* PM_ IO 0x 9A[4] = 0
* PM_ IO 0x 9A[3] = 1 (PM_IO 0x2C/2D setting should be different from PM2_CNT_BLK
* that BIOS reports to OS)
* PM_ IO 0x 8F[5] = 0
* PM_ IO 0x 71[2] = 0
* PM_ IO 0x 71[1] = 0
* PM_ IO 0x 68[1] = 1
* PM_ IO 0x 8D[6] = 0
*/
}
return;
}
