/* Simulates end result of PIFBootROM execution */
void r4300_reset_soft(void)
{
unsigned int rom_type = 0; /* 0:Cart, 1:DD */
unsigned int reset_type = 0; /* 0:ColdReset, 1:NMI */
unsigned int s7 = 0; /* ??? */
unsigned int tv_type = get_tv_type(); /* 0:PAL, 1:NTSC, 2:MPAL */
unsigned int cic_seed = get_cic_seed();
g_cp0_regs[CP0_STATUS_REG] = 0x34000000;
g_cp0_regs[CP0_CONFIG_REG] = 0x0006e463;
sp_register.sp_status_reg = 1;
rsp_register.rsp_pc = 0;
uint32_t bsd_dom1_config = *(uint32_t*)rom;
pi_register.pi_bsd_dom1_lat_reg = (bsd_dom1_config ) & 0xff;
pi_register.pi_bsd_dom1_pwd_reg = (bsd_dom1_config >> 8) & 0xff;
pi_register.pi_bsd_dom1_pgs_reg = (bsd_dom1_config >> 16) & 0x0f;
pi_register.pi_bsd_dom1_rls_reg = (bsd_dom1_config >> 20) & 0x03;
pi_register.read_pi_status_reg = 0;
ai_register.ai_dram_addr = 0;
ai_register.ai_len = 0;
vi_register.vi_v_intr = 1023;
vi_register.vi_current = 0;
vi_register.vi_h_start = 0;
MI_register.mi_intr_reg &= ~(0x10 | 0x8 | 0x4 | 0x1);
memcpy((unsigned char*)SP_DMEM+0x40, rom+0x40, 0xfc0);
reg[19] = rom_type; /* s3 */
reg[20] = tv_type; /* s4 */
reg[21] = reset_type; /* s5 */
reg[22] = cic_seed; /* s6 */
reg[23] = s7; /* s7 */
/* required by CIC x105 */
SP_IMEM[0] = 0x3c0dbfc0;
SP_IMEM[1] = 0x8da807fc;
SP_IMEM[2] = 0x25ad07c0;
SP_IMEM[3] = 0x31080080;
SP_IMEM[4] = 0x5500fffc;
SP_IMEM[5] = 0x3c0dbfc0;
SP_IMEM[6] = 0x8da80024;
SP_IMEM[7] = 0x3c0bb000;
/* required by CIC x105 */
reg[11] = 0xffffffffa4000040ULL; /* t3 */
reg[29] = 0xffffffffa4001ff0ULL; /* sp */
reg[31] = 0xffffffffa4001550ULL; /* ra */
/* ready to execute IPL3 */
}
/* Simulates end result of PIFBootROM execution */
void r4300_reset_soft(void)
{
unsigned int rom_type = 0; /* 0:Cart, 1:DD */
unsigned int reset_type = 0; /* 0:ColdReset, 1:NMI */
unsigned int s7 = 0; /* ??? */
unsigned int tv_type = get_tv_type(); /* 0:PAL, 1:NTSC, 2:MPAL */
uint32_t bsd_dom1_config = *(uint32_t*)g_dev.pi.cart_rom.rom;
g_cp0_regs[CP0_STATUS_REG] = 0x34000000;
g_cp0_regs[CP0_CONFIG_REG] = 0x0006e463;
g_dev.sp.regs[SP_STATUS_REG] = 1;
g_dev.sp.regs2[SP_PC_REG] = 0;
g_dev.pi.regs[PI_BSD_DOM1_LAT_REG] = (bsd_dom1_config ) & 0xff;
g_dev.pi.regs[PI_BSD_DOM1_PWD_REG] = (bsd_dom1_config >> 8) & 0xff;
g_dev.pi.regs[PI_BSD_DOM1_PGS_REG] = (bsd_dom1_config >> 16) & 0x0f;
g_dev.pi.regs[PI_BSD_DOM1_RLS_REG] = (bsd_dom1_config >> 20) & 0x03;
g_dev.pi.regs[PI_STATUS_REG] = 0;
g_dev.ai.regs[AI_DRAM_ADDR_REG] = 0;
g_dev.ai.regs[AI_LEN_REG] = 0;
g_dev.vi.regs[VI_V_INTR_REG] = 1023;
g_dev.vi.regs[VI_CURRENT_REG] = 0;
g_dev.vi.regs[VI_H_START_REG] = 0;
g_dev.r4300.mi.regs[MI_INTR_REG] &= ~(MI_INTR_PI | MI_INTR_VI | MI_INTR_AI | MI_INTR_SP);
memcpy((unsigned char*)g_dev.sp.mem+0x40, g_dev.pi.cart_rom.rom+0x40, 0xfc0);
reg[19] = rom_type; /* s3 */
reg[20] = tv_type; /* s4 */
reg[21] = reset_type; /* s5 */
reg[22] = g_dev.si.pif.cic.seed;/* s6 */
reg[23] = s7; /* s7 */
/* required by CIC x105 */
g_dev.sp.mem[0x1000/4] = 0x3c0dbfc0;
g_dev.sp.mem[0x1004/4] = 0x8da807fc;
g_dev.sp.mem[0x1008/4] = 0x25ad07c0;
g_dev.sp.mem[0x100c/4] = 0x31080080;
g_dev.sp.mem[0x1010/4] = 0x5500fffc;
g_dev.sp.mem[0x1014/4] = 0x3c0dbfc0;
g_dev.sp.mem[0x1018/4] = 0x8da80024;
g_dev.sp.mem[0x101c/4] = 0x3c0bb000;
/* required by CIC x105 */
reg[11] = INT64_C(0xffffffffa4000040); /* t3 */
reg[29] = INT64_C(0xffffffffa4001ff0); /* sp */
reg[31] = INT64_C(0xffffffffa4001550); /* ra */
/* ready to execute IPL3 */
}
/* Simulates end result of PIFBootROM execution */
void r4300_reset_soft(void)
{
uint32_t bsd_dom1_config;
unsigned int rom_type = 0; /* 0:Cart, 1:DD */
unsigned int reset_type = 0; /* 0:ColdReset, 1:NMI */
unsigned int s7 = 0; /* ??? */
unsigned int tv_type = get_tv_type(); /* 0:PAL, 1:NTSC, 2:MPAL */
if ((ConfigGetParamInt(g_CoreConfig, "BootDevice") != 0) && (g_ddrom != NULL) && (g_ddrom_size != 0))
{
bsd_dom1_config = *(uint32_t*)g_ddrom;
rom_type = 1;
}
else
bsd_dom1_config = *(uint32_t*)g_rom;
g_cp0_regs[CP0_STATUS_REG] = 0x34000000;
g_cp0_regs[CP0_CONFIG_REG] = 0x0006e463;
g_sp.regs[SP_STATUS_REG] = 1;
g_sp.regs2[SP_PC_REG] = 0;
g_pi.regs[PI_BSD_DOM1_LAT_REG] = (bsd_dom1_config ) & 0xff;
g_pi.regs[PI_BSD_DOM1_PWD_REG] = (bsd_dom1_config >> 8) & 0xff;
g_pi.regs[PI_BSD_DOM1_PGS_REG] = (bsd_dom1_config >> 16) & 0x0f;
g_pi.regs[PI_BSD_DOM1_RLS_REG] = (bsd_dom1_config >> 20) & 0x03;
g_pi.regs[PI_STATUS_REG] = 0;
g_ai.regs[AI_DRAM_ADDR_REG] = 0;
g_ai.regs[AI_LEN_REG] = 0;
g_vi.regs[VI_V_INTR_REG] = 1023;
g_vi.regs[VI_CURRENT_REG] = 0;
g_vi.regs[VI_H_START_REG] = 0;
g_r4300.mi.regs[MI_INTR_REG] &= ~(MI_INTR_PI | MI_INTR_VI | MI_INTR_AI | MI_INTR_SP);
if ((ConfigGetParamInt(g_CoreConfig, "BootDevice") != 0) && (g_ddrom != NULL) && (g_ddrom_size != 0))
memcpy((unsigned char*)g_sp.mem+0x40, g_ddrom+0x40, 0xfc0);
else
memcpy((unsigned char*)g_sp.mem+0x40, g_rom+0x40, 0xfc0);
reg[19] = rom_type; /* s3 */
reg[20] = tv_type; /* s4 */
reg[21] = reset_type; /* s5 */
reg[22] = g_si.pif.cic.seed; /* s6 */
reg[23] = s7; /* s7 */
if ((ConfigGetParamInt(g_CoreConfig, "BootDevice") != 0) && (g_ddrom != NULL) && (g_ddrom_size != 0))
reg[22] = 0xdd;
/* required by CIC x105 */
g_sp.mem[0x1000/4] = 0x3c0dbfc0;
g_sp.mem[0x1004/4] = 0x8da807fc;
g_sp.mem[0x1008/4] = 0x25ad07c0;
g_sp.mem[0x100c/4] = 0x31080080;
g_sp.mem[0x1010/4] = 0x5500fffc;
g_sp.mem[0x1014/4] = 0x3c0dbfc0;
g_sp.mem[0x1018/4] = 0x8da80024;
g_sp.mem[0x101c/4] = 0x3c0bb000;
/* required by CIC x105 */
reg[11] = 0xffffffffa4000040ULL; /* t3 */
reg[29] = 0xffffffffa4001ff0ULL; /* sp */
reg[31] = 0xffffffffa4001550ULL; /* ra */
/* ready to execute IPL3 */
}
