void local_flush_tlb_all(void) { unsigned long flags; unsigned long old_ctx; int entry; #ifdef DEBUG_TLB printk("[tlball]"); #endif __save_and_cli(flags); /* Save old context and create impossible VPN2 value */ old_ctx = (get_entryhi() & 0xff); set_entryhi(KSEG0); set_entrylo0(0); set_entrylo1(0); BARRIER; entry = get_wired(); /* Blast 'em all away. */ while(entry < mips_cpu.tlbsize) { /* Make sure all entries differ. */ set_entryhi(KSEG0+entry*0x2000); set_index(entry); BARRIER; tlb_write_indexed(); BARRIER; entry++; } BARRIER; set_entryhi(old_ctx); __restore_flags(flags); }
/* TLB operations. */ void local_flush_tlb_all(void) { unsigned long flags; unsigned long old_ctx; int entry; #ifdef DEBUG_TLB printk("[tlball]"); #endif save_and_cli(flags); old_ctx = (get_entryhi() & 0xfc0); write_32bit_cp0_register(CP0_ENTRYLO0, 0); #ifdef CONFIG_CPU_TX39XX entry = r3k_have_wired_reg ? get_wired() : 8; #else entry = 8; #endif for (; entry < mips_cpu.tlbsize; entry++) { write_32bit_cp0_register(CP0_INDEX, entry << 8); write_32bit_cp0_register(CP0_ENTRYHI, ((entry | 0x80000) << 12)); __asm__ __volatile__("tlbwi"); } set_entryhi(old_ctx); restore_flags(flags); }
void dump_tlb_wired(void) { int wired = r3k_have_wired_reg ? get_wired() : 8; printk("Wired: %d", wired); dump_tlb(0, wired - 1); }
void dump_tlb_nonwired(void) { int wired = r3k_have_wired_reg ? get_wired() : 8; dump_tlb(wired, mips_cpu.tlbsize - 1); }