static ssize_t tpc_fs_mask_read(struct device *device,
struct device_attribute *attr, char *buf)
{
struct platform_device *ndev = to_platform_device(device);
struct gk20a *g = get_gk20a(ndev);
struct gr_gk20a *gr = &g->gr;
u32 gpc_index;
u32 tpc_fs_mask = 0;
int err = 0;
err = gk20a_busy(g->dev);
if (err)
return err;
for (gpc_index = 0; gpc_index < gr->gpc_count; gpc_index++) {
if (g->ops.gr.get_gpc_tpc_mask)
tpc_fs_mask |=
g->ops.gr.get_gpc_tpc_mask(g, gpc_index) <<
(gr->max_tpc_per_gpc_count * gpc_index);
}
gk20a_idle(g->dev);
return sprintf(buf, "0x%x\n", tpc_fs_mask);
}
static ssize_t elpg_enable_store(struct device *device,
struct device_attribute *attr, const char *buf, size_t count)
{
struct platform_device *ndev = to_platform_device(device);
struct gk20a *g = get_gk20a(ndev);
unsigned long val = 0;
int err;
if (kstrtoul(buf, 10, &val) < 0)
return -EINVAL;
/*
* Since elpg is refcounted, we should not unnecessarily call
* enable/disable if it is already so.
*/
err = gk20a_busy(g->dev);
if (err)
return -EAGAIN;
if (val && !g->elpg_enabled) {
g->elpg_enabled = true;
gk20a_pmu_enable_elpg(g);
} else if (!val && g->elpg_enabled) {
g->elpg_enabled = false;
gk20a_pmu_disable_elpg(g);
}
gk20a_idle(g->dev);
dev_info(device, "ELPG is %s.\n", g->elpg_enabled ? "enabled" :
"disabled");
return count;
}
static ssize_t elcg_enable_store(struct device *device,
struct device_attribute *attr, const char *buf, size_t count)
{
struct platform_device *ndev = to_platform_device(device);
struct gk20a *g = get_gk20a(ndev);
unsigned long val = 0;
int err;
if (kstrtoul(buf, 10, &val) < 0)
return -EINVAL;
err = gk20a_busy(g->dev);
if (err)
return err;
if (val) {
g->elcg_enabled = true;
gr_gk20a_init_elcg_mode(g, ELCG_AUTO, ENGINE_GR_GK20A);
gr_gk20a_init_elcg_mode(g, ELCG_AUTO, ENGINE_CE2_GK20A);
} else {
g->elcg_enabled = false;
gr_gk20a_init_elcg_mode(g, ELCG_RUN, ENGINE_GR_GK20A);
gr_gk20a_init_elcg_mode(g, ELCG_RUN, ENGINE_CE2_GK20A);
}
gk20a_idle(g->dev);
dev_info(device, "ELCG is %s.\n", g->elcg_enabled ? "enabled" :
"disabled");
return count;
}
static ssize_t gk20a_load_show(struct device *dev,
struct device_attribute *attr,
char *buf)
{
struct platform_device *pdev = to_platform_device(dev);
struct gk20a *g = get_gk20a(pdev);
u32 busy_time;
ssize_t res;
int err;
if (!g->power_on) {
busy_time = 0;
} else {
err = gk20a_busy(g->dev);
if (err)
return err;
gk20a_pmu_load_update(g);
gk20a_pmu_load_norm(g, &busy_time);
gk20a_idle(g->dev);
}
res = snprintf(buf, PAGE_SIZE, "%u\n", busy_time);
return res;
}
static int monitor_get(void *data, u64 *val)
{
struct gk20a *g = (struct gk20a *)data;
struct clk_gk20a *clk = &g->clk;
u32 ncycle = 100; /* count GPCCLK for ncycle of clkin */
u32 clkin = clk->gpc_pll.clk_in;
u32 count1, count2;
gk20a_busy(g->dev);
gk20a_writel(g, trim_gpc_clk_cntr_ncgpcclk_cfg_r(0),
trim_gpc_clk_cntr_ncgpcclk_cfg_reset_asserted_f());
gk20a_writel(g, trim_gpc_clk_cntr_ncgpcclk_cfg_r(0),
trim_gpc_clk_cntr_ncgpcclk_cfg_enable_asserted_f() |
trim_gpc_clk_cntr_ncgpcclk_cfg_write_en_asserted_f() |
trim_gpc_clk_cntr_ncgpcclk_cfg_noofipclks_f(ncycle));
/* start */
/* It should take about 8us to finish 100 cycle of 12MHz.
But longer than 100us delay is required here. */
gk20a_readl(g, trim_gpc_clk_cntr_ncgpcclk_cfg_r(0));
udelay(2000);
count1 = gk20a_readl(g, trim_gpc_clk_cntr_ncgpcclk_cnt_r(0));
udelay(100);
count2 = gk20a_readl(g, trim_gpc_clk_cntr_ncgpcclk_cnt_r(0));
*val = (u64)(trim_gpc_clk_cntr_ncgpcclk_cnt_value_v(count2) * clkin / ncycle);
gk20a_idle(g->dev);
if (count1 != count2)
return -EBUSY;
return 0;
}
static ssize_t slcg_enable_store(struct device *device,
struct device_attribute *attr, const char *buf, size_t count)
{
struct platform_device *ndev = to_platform_device(device);
struct gk20a *g = get_gk20a(ndev);
unsigned long val = 0;
int err;
if (kstrtoul(buf, 10, &val) < 0)
return -EINVAL;
if (val)
g->slcg_enabled = true;
else
g->slcg_enabled = false;
/*
* TODO: slcg_therm_load_gating is not enabled anywhere during
* init. Therefore, it would be incongruous to add it here. Once
* it is added to init, we should add it here too.
*/
err = gk20a_busy(g->dev);
if (err)
return err;
if (g->ops.clock_gating.slcg_bus_load_gating_prod)
g->ops.clock_gating.slcg_bus_load_gating_prod(g, g->slcg_enabled);
if (g->ops.clock_gating.slcg_ce2_load_gating_prod)
g->ops.clock_gating.slcg_ce2_load_gating_prod(g, g->slcg_enabled);
if (g->ops.clock_gating.slcg_chiplet_load_gating_prod)
g->ops.clock_gating.slcg_chiplet_load_gating_prod(g, g->slcg_enabled);
if (g->ops.clock_gating.slcg_ctxsw_firmware_load_gating_prod)
g->ops.clock_gating.slcg_ctxsw_firmware_load_gating_prod(g, g->slcg_enabled);
if (g->ops.clock_gating.slcg_fb_load_gating_prod)
g->ops.clock_gating.slcg_fb_load_gating_prod(g, g->slcg_enabled);
if (g->ops.clock_gating.slcg_fifo_load_gating_prod)
g->ops.clock_gating.slcg_fifo_load_gating_prod(g, g->slcg_enabled);
g->ops.clock_gating.slcg_gr_load_gating_prod(g, g->slcg_enabled);
if (g->ops.clock_gating.slcg_ltc_load_gating_prod)
g->ops.clock_gating.slcg_ltc_load_gating_prod(g, g->slcg_enabled);
g->ops.clock_gating.slcg_perf_load_gating_prod(g, g->slcg_enabled);
if (g->ops.clock_gating.slcg_priring_load_gating_prod)
g->ops.clock_gating.slcg_priring_load_gating_prod(g, g->slcg_enabled);
if (g->ops.clock_gating.slcg_pmu_load_gating_prod)
g->ops.clock_gating.slcg_pmu_load_gating_prod(g, g->slcg_enabled);
if (g->ops.clock_gating.slcg_xbar_load_gating_prod)
g->ops.clock_gating.slcg_xbar_load_gating_prod(g, g->slcg_enabled);
gk20a_idle(g->dev);
dev_info(device, "SLCG is %s.\n", g->slcg_enabled ? "enabled" :
"disabled");
return count;
}
static int gk20a_ctrl_prepare_compressible_read(
struct gk20a *g,
struct nvgpu_gpu_prepare_compressible_read_args *args)
{
struct nvgpu_fence fence;
struct gk20a_fence *fence_out = NULL;
int ret = 0;
int flags = args->submit_flags;
fence.id = args->fence.syncpt_id;
fence.value = args->fence.syncpt_value;
ret = gk20a_busy(g->dev);
if (ret)
return ret;
ret = gk20a_prepare_compressible_read(g, args->handle,
args->request_compbits, args->offset,
args->compbits_hoffset, args->compbits_voffset,
args->width, args->height, args->block_height_log2,
flags, &fence, &args->valid_compbits,
&args->zbc_color, &fence_out);
gk20a_idle(g->dev);
if (ret)
return ret;
/* Convert fence_out to something we can pass back to user space. */
if (flags & NVGPU_SUBMIT_GPFIFO_FLAGS_FENCE_GET) {
if (flags & NVGPU_SUBMIT_GPFIFO_FLAGS_SYNC_FENCE) {
if (fence_out) {
int fd = gk20a_fence_install_fd(fence_out);
if (fd < 0)
ret = fd;
else
args->fence.fd = fd;
} else {
args->fence.fd = -1;
}
} else {
if (fence_out) {
args->fence.syncpt_id = fence_out->syncpt_id;
args->fence.syncpt_value =
fence_out->syncpt_value;
} else {
args->fence.syncpt_id = -1;
args->fence.syncpt_value = 0;
}
}
}
gk20a_fence_put(fence_out);
return 0;
}
static int gk20a_ctrl_mark_compressible_write(
struct gk20a *g,
struct nvgpu_gpu_mark_compressible_write_args *args)
{
int ret;
ret = gk20a_busy(g->dev);
if (ret)
return ret;
ret = gk20a_mark_compressible_write(g, args->handle,
args->valid_compbits, args->offset, args->zbc_color);
gk20a_idle(g->dev);
return ret;
}
static ssize_t allow_all_enable_store(struct device *device,
struct device_attribute *attr, const char *buf, size_t count)
{
struct platform_device *ndev = to_platform_device(device);
struct gk20a *g = get_gk20a(ndev);
unsigned long val = 0;
int err;
if (kstrtoul(buf, 10, &val) < 0)
return -EINVAL;
err = gk20a_busy(g->dev);
g->allow_all = (val ? true : false);
gk20a_idle(g->dev);
return count;
}
static ssize_t blcg_enable_store(struct device *device,
struct device_attribute *attr, const char *buf, size_t count)
{
struct platform_device *ndev = to_platform_device(device);
struct gk20a *g = get_gk20a(ndev);
unsigned long val = 0;
int err;
if (kstrtoul(buf, 10, &val) < 0)
return -EINVAL;
if (val)
g->blcg_enabled = true;
else
g->blcg_enabled = false;
err = gk20a_busy(g->dev);
if (err)
return err;
if (g->ops.clock_gating.blcg_bus_load_gating_prod)
g->ops.clock_gating.blcg_bus_load_gating_prod(g, g->blcg_enabled);
if (g->ops.clock_gating.blcg_ctxsw_firmware_load_gating_prod)
g->ops.clock_gating.blcg_ctxsw_firmware_load_gating_prod(g, g->blcg_enabled);
if (g->ops.clock_gating.blcg_fb_load_gating_prod)
g->ops.clock_gating.blcg_fb_load_gating_prod(g, g->blcg_enabled);
if (g->ops.clock_gating.blcg_fifo_load_gating_prod)
g->ops.clock_gating.blcg_fifo_load_gating_prod(g, g->blcg_enabled);
g->ops.clock_gating.blcg_gr_load_gating_prod(g, g->blcg_enabled);
if (g->ops.clock_gating.blcg_ltc_load_gating_prod)
g->ops.clock_gating.blcg_ltc_load_gating_prod(g, g->blcg_enabled);
if (g->ops.clock_gating.blcg_pmu_load_gating_prod)
g->ops.clock_gating.blcg_pmu_load_gating_prod(g, g->blcg_enabled);
gk20a_idle(g->dev);
dev_info(device, "BLCG is %s.\n", g->blcg_enabled ? "enabled" :
"disabled");
return count;
}
static ssize_t aelpg_enable_store(struct device *device,
struct device_attribute *attr, const char *buf, size_t count)
{
struct platform_device *ndev = to_platform_device(device);
struct gk20a *g = get_gk20a(ndev);
unsigned long val = 0;
int status = 0;
union pmu_ap_cmd ap_cmd;
int err;
if (kstrtoul(buf, 10, &val) < 0)
return -EINVAL;
err = gk20a_busy(g->dev);
if (err)
return err;
if (g->pmu.pmu_ready) {
if (val && !g->aelpg_enabled) {
g->aelpg_enabled = true;
/* Enable AELPG */
ap_cmd.init.cmd_id = PMU_AP_CMD_ID_ENABLE_CTRL;
status = gk20a_pmu_ap_send_command(g, &ap_cmd, false);
} else if (!val && g->aelpg_enabled) {
g->aelpg_enabled = false;
/* Disable AELPG */
ap_cmd.init.cmd_id = PMU_AP_CMD_ID_DISABLE_CTRL;
status = gk20a_pmu_ap_send_command(g, &ap_cmd, false);
}
} else {
dev_info(device, "PMU is not ready, AELPG request failed\n");
}
gk20a_idle(g->dev);
dev_info(device, "AELPG is %s.\n", g->aelpg_enabled ? "enabled" :
"disabled");
return count;
}
long gk20a_ctrl_dev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
{
struct platform_device *dev = filp->private_data;
struct gk20a *g = get_gk20a(dev);
struct nvhost_gpu_zcull_get_ctx_size_args *get_ctx_size_args;
struct nvhost_gpu_zcull_get_info_args *get_info_args;
struct nvhost_gpu_zbc_set_table_args *set_table_args;
struct nvhost_gpu_zbc_query_table_args *query_table_args;
u8 buf[NVHOST_GPU_IOCTL_MAX_ARG_SIZE];
struct gr_zcull_info *zcull_info;
struct zbc_entry *zbc_val;
struct zbc_query_params *zbc_tbl;
int i, err = 0;
nvhost_dbg_fn("");
if ((_IOC_TYPE(cmd) != NVHOST_GPU_IOCTL_MAGIC) ||
(_IOC_NR(cmd) == 0) ||
(_IOC_NR(cmd) > NVHOST_GPU_IOCTL_LAST))
return -EFAULT;
BUG_ON(_IOC_SIZE(cmd) > NVHOST_GPU_IOCTL_MAX_ARG_SIZE);
if (_IOC_DIR(cmd) & _IOC_WRITE) {
if (copy_from_user(buf, (void __user *)arg, _IOC_SIZE(cmd)))
return -EFAULT;
}
if (!g->gr.sw_ready) {
gk20a_busy(g->dev);
gk20a_idle(g->dev);
}
switch (cmd) {
case NVHOST_GPU_IOCTL_ZCULL_GET_CTX_SIZE:
get_ctx_size_args = (struct nvhost_gpu_zcull_get_ctx_size_args *)buf;
get_ctx_size_args->size = gr_gk20a_get_ctxsw_zcull_size(g, &g->gr);
break;
case NVHOST_GPU_IOCTL_ZCULL_GET_INFO:
get_info_args = (struct nvhost_gpu_zcull_get_info_args *)buf;
memset(get_info_args, 0, sizeof(struct nvhost_gpu_zcull_get_info_args));
zcull_info = kzalloc(sizeof(struct gr_zcull_info), GFP_KERNEL);
if (zcull_info == NULL)
return -ENOMEM;
err = gr_gk20a_get_zcull_info(g, &g->gr, zcull_info);
if (err)
break;
get_info_args->width_align_pixels = zcull_info->width_align_pixels;
get_info_args->height_align_pixels = zcull_info->height_align_pixels;
get_info_args->pixel_squares_by_aliquots = zcull_info->pixel_squares_by_aliquots;
get_info_args->aliquot_total = zcull_info->aliquot_total;
get_info_args->region_byte_multiplier = zcull_info->region_byte_multiplier;
get_info_args->region_header_size = zcull_info->region_header_size;
get_info_args->subregion_header_size = zcull_info->subregion_header_size;
get_info_args->subregion_width_align_pixels = zcull_info->subregion_width_align_pixels;
get_info_args->subregion_height_align_pixels = zcull_info->subregion_height_align_pixels;
get_info_args->subregion_count = zcull_info->subregion_count;
if (zcull_info)
kfree(zcull_info);
break;
case NVHOST_GPU_IOCTL_ZBC_SET_TABLE:
set_table_args = (struct nvhost_gpu_zbc_set_table_args *)buf;
zbc_val = kzalloc(sizeof(struct zbc_entry), GFP_KERNEL);
if (zbc_val == NULL)
return -ENOMEM;
zbc_val->format = set_table_args->format;
zbc_val->type = set_table_args->type;
switch (zbc_val->type) {
case GK20A_ZBC_TYPE_COLOR:
for (i = 0; i < GK20A_ZBC_COLOR_VALUE_SIZE; i++) {
zbc_val->color_ds[i] = set_table_args->color_ds[i];
zbc_val->color_l2[i] = set_table_args->color_l2[i];
}
break;
case GK20A_ZBC_TYPE_DEPTH:
zbc_val->depth = set_table_args->depth;
break;
default:
err = -EINVAL;
}
if (!err) {
gk20a_busy(dev);
err = gk20a_gr_zbc_set_table(g, &g->gr, zbc_val);
gk20a_idle(dev);
}
if (zbc_val)
kfree(zbc_val);
break;
case NVHOST_GPU_IOCTL_ZBC_QUERY_TABLE:
query_table_args = (struct nvhost_gpu_zbc_query_table_args *)buf;
zbc_tbl = kzalloc(sizeof(struct zbc_query_params), GFP_KERNEL);
if (zbc_tbl == NULL)
return -ENOMEM;
zbc_tbl->type = query_table_args->type;
zbc_tbl->index_size = query_table_args->index_size;
err = gr_gk20a_query_zbc(g, &g->gr, zbc_tbl);
if (!err) {
switch (zbc_tbl->type) {
case GK20A_ZBC_TYPE_COLOR:
for (i = 0; i < GK20A_ZBC_COLOR_VALUE_SIZE; i++) {
query_table_args->color_ds[i] = zbc_tbl->color_ds[i];
query_table_args->color_l2[i] = zbc_tbl->color_l2[i];
}
break;
case GK20A_ZBC_TYPE_DEPTH:
query_table_args->depth = zbc_tbl->depth;
break;
case GK20A_ZBC_TYPE_INVALID:
query_table_args->index_size = zbc_tbl->index_size;
break;
default:
err = -EINVAL;
}
if (!err) {
query_table_args->format = zbc_tbl->format;
query_table_args->ref_cnt = zbc_tbl->ref_cnt;
}
}
if (zbc_tbl)
kfree(zbc_tbl);
break;
case NVHOST_GPU_IOCTL_GET_CHARACTERISTICS:
err = gk20a_ctrl_ioctl_gpu_characteristics(
g, (struct nvhost_gpu_get_characteristics *)buf);
break;
default:
nvhost_err(dev_from_gk20a(g), "unrecognized gpu ioctl cmd: 0x%x", cmd);
err = -ENOTTY;
break;
}
if ((err == 0) && (_IOC_DIR(cmd) & _IOC_READ))
err = copy_to_user((void __user *)arg, buf, _IOC_SIZE(cmd));
return err;
}
static void gk20a_debug_show_dump(struct platform_device *pdev,
struct gk20a_debug_output *o)
{
struct gk20a_platform *platform = gk20a_get_platform(pdev);
struct gk20a *g = platform->g;
struct fifo_gk20a *f = &g->fifo;
u32 chid;
int i, err;
err = gk20a_busy(g->dev);
if (err) {
gk20a_debug_output(o, "failed to power on gpu: %d\n", err);
return;
}
for (i = 0; i < fifo_pbdma_status__size_1_v(); i++) {
u32 status = gk20a_readl(g, fifo_pbdma_status_r(i));
u32 chan_status = fifo_pbdma_status_chan_status_v(status);
gk20a_debug_output(o, "%s pbdma %d: ", g->dev->name, i);
gk20a_debug_output(o,
"id: %d (%s), next_id: %d (%s) status: %s\n",
fifo_pbdma_status_id_v(status),
fifo_pbdma_status_id_type_v(status) ?
"tsg" : "channel",
fifo_pbdma_status_next_id_v(status),
fifo_pbdma_status_next_id_type_v(status) ?
"tsg" : "channel",
chan_status_str[chan_status]);
gk20a_debug_output(o, "PUT: %016llx GET: %016llx "
"FETCH: %08x HEADER: %08x\n",
(u64)gk20a_readl(g, pbdma_put_r(i)) +
((u64)gk20a_readl(g, pbdma_put_hi_r(i)) << 32ULL),
(u64)gk20a_readl(g, pbdma_get_r(i)) +
((u64)gk20a_readl(g, pbdma_get_hi_r(i)) << 32ULL),
gk20a_readl(g, pbdma_gp_fetch_r(i)),
gk20a_readl(g, pbdma_pb_header_r(i)));
}
gk20a_debug_output(o, "\n");
for (i = 0; i < fifo_engine_status__size_1_v(); i++) {
u32 status = gk20a_readl(g, fifo_engine_status_r(i));
u32 ctx_status = fifo_engine_status_ctx_status_v(status);
gk20a_debug_output(o, "%s eng %d: ", g->dev->name, i);
gk20a_debug_output(o,
"id: %d (%s), next_id: %d (%s), ctx: %s ",
fifo_engine_status_id_v(status),
fifo_engine_status_id_type_v(status) ?
"tsg" : "channel",
fifo_engine_status_next_id_v(status),
fifo_engine_status_next_id_type_v(status) ?
"tsg" : "channel",
ctx_status_str[ctx_status]);
if (fifo_engine_status_faulted_v(status))
gk20a_debug_output(o, "faulted ");
if (fifo_engine_status_engine_v(status))
gk20a_debug_output(o, "busy ");
gk20a_debug_output(o, "\n");
}
gk20a_debug_output(o, "\n");
for (chid = 0; chid < f->num_channels; chid++) {
if (f->channel[chid].in_use) {
struct channel_gk20a *gpu_ch = &f->channel[chid];
gk20a_debug_show_channel(g, o, gpu_ch);
}
}
gk20a_idle(g->dev);
}
long gk20a_as_dev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
{
int err = 0;
struct gk20a_as_share *as_share = filp->private_data;
struct gk20a *g = gk20a_from_as(as_share->as);
u8 buf[NVHOST_AS_IOCTL_MAX_ARG_SIZE];
if ((_IOC_TYPE(cmd) != NVHOST_AS_IOCTL_MAGIC) ||
(_IOC_NR(cmd) == 0) ||
(_IOC_NR(cmd) > NVHOST_AS_IOCTL_LAST))
return -EFAULT;
BUG_ON(_IOC_SIZE(cmd) > NVHOST_AS_IOCTL_MAX_ARG_SIZE);
if (_IOC_DIR(cmd) & _IOC_WRITE) {
if (copy_from_user(buf, (void __user *)arg, _IOC_SIZE(cmd)))
return -EFAULT;
}
err = gk20a_busy(g->dev);
if (err)
return err;
switch (cmd) {
case NVHOST_AS_IOCTL_BIND_CHANNEL:
trace_gk20a_as_ioctl_bind_channel(dev_name(dev_from_gk20a(g)));
err = gk20a_as_ioctl_bind_channel(as_share,
(struct nvhost_as_bind_channel_args *)buf);
break;
case NVHOST32_AS_IOCTL_ALLOC_SPACE:
{
struct nvhost32_as_alloc_space_args *args32 =
(struct nvhost32_as_alloc_space_args *)buf;
struct nvhost_as_alloc_space_args args;
args.pages = args32->pages;
args.page_size = args32->page_size;
args.flags = args32->flags;
args.o_a.offset = args32->o_a.offset;
trace_gk20a_as_ioctl_alloc_space(dev_name(dev_from_gk20a(g)));
err = gk20a_as_ioctl_alloc_space(as_share, &args);
args32->o_a.offset = args.o_a.offset;
break;
}
case NVHOST_AS_IOCTL_ALLOC_SPACE:
trace_gk20a_as_ioctl_alloc_space(dev_name(dev_from_gk20a(g)));
err = gk20a_as_ioctl_alloc_space(as_share,
(struct nvhost_as_alloc_space_args *)buf);
break;
case NVHOST_AS_IOCTL_FREE_SPACE:
trace_gk20a_as_ioctl_free_space(dev_name(dev_from_gk20a(g)));
err = gk20a_as_ioctl_free_space(as_share,
(struct nvhost_as_free_space_args *)buf);
break;
case NVHOST_AS_IOCTL_MAP_BUFFER:
trace_gk20a_as_ioctl_map_buffer(dev_name(dev_from_gk20a(g)));
err = gk20a_as_ioctl_map_buffer(as_share,
(struct nvhost_as_map_buffer_args *)buf);
break;
case NVHOST_AS_IOCTL_MAP_BUFFER_EX:
trace_gk20a_as_ioctl_map_buffer(dev_name(dev_from_gk20a(g)));
err = gk20a_as_ioctl_map_buffer_ex(as_share,
(struct nvhost_as_map_buffer_ex_args *)buf);
break;
case NVHOST_AS_IOCTL_UNMAP_BUFFER:
trace_gk20a_as_ioctl_unmap_buffer(dev_name(dev_from_gk20a(g)));
err = gk20a_as_ioctl_unmap_buffer(as_share,
(struct nvhost_as_unmap_buffer_args *)buf);
break;
default:
dev_err(dev_from_gk20a(g), "unrecognized as ioctl: 0x%x", cmd);
err = -ENOTTY;
break;
}
gk20a_idle(g->dev);
if ((err == 0) && (_IOC_DIR(cmd) & _IOC_READ))
err = copy_to_user((void __user *)arg, buf, _IOC_SIZE(cmd));
return err;
}