bool gmac_configure(Gmac* gmac)
{
pmc_enable_peripheral(get_gmac_id_from_addr(gmac));
/* Disable TX & RX and more */
gmac_set_network_control_register(gmac, 0);
gmac_set_network_config_register(gmac, GMAC_NCFGR_DBW_DBW32);
/* Disable interrupts */
gmac_disable_it(gmac, 0, ~0u);
#ifdef CONFIG_HAVE_GMAC_QUEUES
gmac_disable_it(gmac, 1, ~0u);
gmac_disable_it(gmac, 2, ~0u);
#endif
/* Clear statistics */
gmac_clear_statistics(gmac);
/* Clear all status bits in the receive status register. */
gmac_clear_rx_status(gmac, GMAC_RSR_RXOVR | GMAC_RSR_REC |
GMAC_RSR_BNA | GMAC_RSR_HNO);
/* Clear all status bits in the transmit status register */
gmac_clear_tx_status(gmac, GMAC_TSR_UBR | GMAC_TSR_COL |
GMAC_TSR_RLE | GMAC_TSR_TXGO | GMAC_TSR_TFC |
GMAC_TSR_TXCOMP | GMAC_TSR_UND | GMAC_TSR_HRESP);
/* Clear interrupts */
gmac_get_it_status(gmac, 0);
#ifdef CONFIG_HAVE_GMAC_QUEUES
gmac_get_it_status(gmac, 1);
gmac_get_it_status(gmac, 2);
#endif
return _gmac_configure_mdc_clock(gmac);
}
/**
* \brief GMAC Interrupt handler
* \param gmacd Pointer to GMAC Driver instance.
*/
static void _gmacd_handler(struct _gmacd * gmacd, uint8_t queue)
{
Gmac *gmac = gmacd->gmac;
struct _gmacd_queue* q = &gmacd->queues[queue];
uint32_t isr;
uint32_t rsr;
/* Interrupt Status Register is cleared on read */
while ((isr = gmac_get_it_status(gmac, queue)) != 0) {
/* RX packet */
if (isr & GMAC_INT_RX_BITS) {
/* Clear status */
rsr = gmac_get_rx_status(gmac);
gmac_clear_rx_status(gmac, rsr);
/* Invoke callback */
if (q->rx_callback)
q->rx_callback(queue, rsr);
}
/* TX error */
if (isr & GMAC_INT_TX_ERR_BITS) {
_gmacd_tx_error_handler(gmacd, queue);
break;
}
/* TX packet */
if (isr & GMAC_IER_TCOMP) {
_gmacd_tx_complete_handler(gmacd, queue);
}
/* HRESP not OK */
if (isr & GMAC_IER_HRESP) {
trace_error("HRESP not OK\n\r");
}
}
}
