void __init wx5800_pci_hw_init(void) { /* Disable PCI clock */ *IXP425_GPIO_GPCLKR &= ~IXP425_PCI_CLK_ENABLE; /* configure PCI-related GPIO */ gpio_line_config(IXP425_PCI_CLK_PIN, IXP425_GPIO_OUT); gpio_line_config(IXP425_PCI_RESET_GPIO, IXP425_GPIO_OUT); gpio_line_config(IXP425_PCI_INTA_GPIO, IXP425_GPIO_IN | IXP425_GPIO_ACTIVE_LOW); gpio_line_config(IXP425_PCI_INTB_GPIO, IXP425_GPIO_IN | IXP425_GPIO_ACTIVE_LOW); gpio_line_isr_clear(IXP425_PCI_INTA_GPIO); gpio_line_isr_clear(IXP425_PCI_INTB_GPIO); /* Assert reset for PCI controller */ gpio_line_set(IXP425_PCI_RESET_GPIO, IXP425_GPIO_LOW); /* wait 1ms to satisfy "minimum reset assertion time" of the PCI spec. */ udelay(1000); /* Config PCI clock */ *IXP425_GPIO_GPCLKR |= (0xf << IXP425_PCI_CLK_TC_LSH) | (0xf << IXP425_PCI_CLK_DC_LSH); /* Enable PCI clock */ *IXP425_GPIO_GPCLKR |= IXP425_PCI_CLK_ENABLE; /* wait 100us to satisfy "minimum reset assertion time from clock stable" * requirement of the PCI spec. */ udelay(100); /* Deassert reset for PCI controller */ gpio_line_set(IXP425_PCI_RESET_GPIO, IXP425_GPIO_HIGH); /* wait a while to let other devices get ready after PCI reset */ udelay(1000); }
void __init coyote_pci_preinit(void) { gpio_line_config(COYOTE_PCI_SLOT0_PIN, IXP4XX_GPIO_IN | IXP4XX_GPIO_ACTIVE_LOW); gpio_line_config(COYOTE_PCI_SLOT1_PIN, IXP4XX_GPIO_IN | IXP4XX_GPIO_ACTIVE_LOW); gpio_line_isr_clear(COYOTE_PCI_SLOT0_PIN); gpio_line_isr_clear(COYOTE_PCI_SLOT1_PIN); ixp4xx_pci_preinit(); }
void __init bruce_pci_gpio_init(void) { /* configure PCI-related GPIO */ gpio_line_config(USB_GPIO, IXP425_GPIO_IN | IXP425_GPIO_ACTIVE_LOW); gpio_line_config(PATA_GPIO, IXP425_GPIO_IN | IXP425_GPIO_ACTIVE_LOW); gpio_line_config(SATA_GPIO, IXP425_GPIO_IN | IXP425_GPIO_ACTIVE_LOW); gpio_line_config(MINIPCI_GPIO, IXP425_GPIO_IN | IXP425_GPIO_ACTIVE_LOW); gpio_line_isr_clear(USB_GPIO); gpio_line_isr_clear(PATA_GPIO); gpio_line_isr_clear(SATA_GPIO); gpio_line_isr_clear(MINIPCI_GPIO); }
void __init coyote_pci_init(void *sysdata) { #ifdef CONFIG_PCI_RESET if (ixp425_pci_is_host()) coyote_pci_hw_init(); #endif gpio_line_config(IXP425_GPIO_PIN_11, IXP425_GPIO_IN | IXP425_GPIO_ACTIVE_LOW); gpio_line_config(IXP425_GPIO_PIN_6, IXP425_GPIO_IN | IXP425_GPIO_ACTIVE_LOW); gpio_line_isr_clear(IXP425_GPIO_PIN_11); gpio_line_isr_clear(IXP425_GPIO_PIN_6); ixp425_pci_init(sysdata); }
static int __init fiq_init(void) { printk("FIQ: installing ERASE button debug FIQ handler\n"); #if 0 printk("CURRENT FIQ = %08x\n", *((unsigned int *) FIQ_VECTOR)); #endif /* Configure Erase switch as IRQ/FIQ input */ gpio_line_config(ERASEGPIO, (IXP4XX_GPIO_IN)); set_irq_type(ERASEIRQ, IRQT_FALLING); gpio_line_isr_clear(ERASEGPIO); *IXP4XX_ICLR |= (1 << ERASEIRQ); unprotect_page_0(); memcpy(FIQ_VECTOR, fiqasm, 96); protect_page_0(); flush_icache_range(FIQ_VECTOR, FIQ_VECTOR + 96); #if 0 printk("CURRENT FIQ = %08x\n", *((unsigned int *) FIQ_VECTOR)); #endif return 0; }
static void ivpnss_isr(int irq, void *dev_id, struct pt_regs *regs) { gpio_line_isr_clear(IXP425_GPIO_PIN_7); if (ivpnss_handler) ivpnss_handler(irq, dev_id, regs); }
void __init montejade_pci_init(void *sysdata) { printk("PCI: reset bus...\n"); gpio_line_set(IXP425_GPIO_PIN_8, 0); gpio_line_config(IXP425_GPIO_PIN_8, IXP425_GPIO_OUT); gpio_line_set(IXP425_GPIO_PIN_8, 0); mdelay(50); gpio_line_set(IXP425_GPIO_PIN_8, 1); mdelay(50); gpio_line_config(INTA_PIN, IXP425_GPIO_IN | IXP425_GPIO_ACTIVE_LOW); gpio_line_config(INTB_PIN, IXP425_GPIO_IN | IXP425_GPIO_ACTIVE_LOW); gpio_line_isr_clear(INTA_PIN); gpio_line_isr_clear(INTB_PIN); ixp425_pci_init(sysdata); }
void __init prpmc1100_pci_preinit(void) { gpio_line_config(PRPMC1100_PCI_INTA_PIN, IXP4XX_GPIO_IN | IXP4XX_GPIO_ACTIVE_LOW); gpio_line_config(PRPMC1100_PCI_INTB_PIN, IXP4XX_GPIO_IN | IXP4XX_GPIO_ACTIVE_LOW); gpio_line_config(PRPMC1100_PCI_INTC_PIN, IXP4XX_GPIO_IN | IXP4XX_GPIO_ACTIVE_LOW); gpio_line_config(PRPMC1100_PCI_INTD_PIN, IXP4XX_GPIO_IN | IXP4XX_GPIO_ACTIVE_LOW); gpio_line_isr_clear(PRPMC1100_PCI_INTA_PIN); gpio_line_isr_clear(PRPMC1100_PCI_INTB_PIN); gpio_line_isr_clear(PRPMC1100_PCI_INTC_PIN); gpio_line_isr_clear(PRPMC1100_PCI_INTD_PIN); ixp4xx_pci_preinit(); }
static void ixp425_irq_mask_ack(unsigned int irq) { static int irq2gpio[NR_IRQS] = { -1, -1, -1, -1, -1, -1, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, -1, -1, }; int line = irq2gpio[irq]; if (line > 0) gpio_line_isr_clear(line); ixp425_irq_mask(irq); }
void ivpnss_hwsetup(void) { int i; if (ivpnss_hwinited) return; /* Setup IXP4xx chip selects, CS1 is for 8bit, CS2 is 16bit */ *IXP425_EXP_CS1 = 0x97d10c03; *IXP425_EXP_CS2 = 0x97d10c02; /* expansion bus speeds */ // *IXP425_GPIO_GPCLKR = (*IXP425_GPIO_GPCLKR & 0x0000ffff) | 0x01420000; /* Setup IRQ line, we use GPIO7 which maps tp IRQ 24 */ gpio_line_config(IXP425_GPIO_PIN_7, (IXP425_GPIO_IN | IXP425_GPIO_FALLING_EDGE)); gpio_line_isr_clear(IXP425_GPIO_PIN_7); /* Setup PCMCIA/CF REG line (for accessing attribute space) */ gpio_line_config(IXP425_GPIO_PIN_10, IXP425_GPIO_OUT); gpio_line_set(IXP425_GPIO_PIN_10, 1); /* Setup PCMCIA/CF IO/MEM (confusingly called RD/WR) select */ gpio_line_config(IXP425_GPIO_PIN_8, IXP425_GPIO_OUT); gpio_line_set(IXP425_GPIO_PIN_10, 1); /* Setup PCMCIA/CF RESET line, and issue a short reset */ gpio_line_set(IXP425_GPIO_PIN_6, 0); gpio_line_config(IXP425_GPIO_PIN_6, IXP425_GPIO_OUT); /* for (i = 0; (i < 100); i++) udelay(1000); gpio_line_set(IXP425_GPIO_PIN_6, 1); */ /* Leave the region idling in "attribute" mode */ ivpnss_mem_mode = MODE_ATTRIBUTE; ivpnss_enable_attribute(); ivpnss_hwinited = 1; }
static void ixp4xx_irq_unmask(unsigned int irq) { static int irq2gpio[NR_IRQS] = { -1, -1, -1, -1, -1, -1, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, -1, -1, }; int line = irq2gpio[irq]; /* * This only works for LEVEL gpio IRQs as per the IXP4xx developer's * manual. If edge-triggered, need to move it to the mask_ack. * Nobody seems to be using the edge-triggered mode on the GPIOs. */ if (line >= 0) gpio_line_isr_clear(line); *IXP4XX_ICMR |= (1 << irq); }
void __init avila_ide_init(void) { hw_regs_t hw; ide_hwif_t *hwif; unsigned char *avila_ide_iobase; int i; gpio_line_config(AVILA_IDE_INT, IXP4XX_GPIO_IN | IXP4XX_GPIO_STYLE_ACTIVE_HIGH); gpio_line_isr_clear(AVILA_IDE_INT); *IXP4XX_EXP_CS1 |= AVILA_IDE_CS1_BITS; avila_ide_iobase = ioremap(AVILA_IDE_BASE, 0x1000); memset(&hw, 0, sizeof(hw)); hw.irq = AVILA_IDE_IRQ; hw.dma = NO_DMA; for (i = 0; (i <= IDE_STATUS_OFFSET); i++) hw.io_ports[i] = (unsigned long)(avila_ide_iobase + i); hw.io_ports[IDE_CONTROL_OFFSET] = (unsigned long)(avila_ide_iobase + AVILA_IDE_CONTROL); printk("ide: Gateworks Avila IDE/CF driver v1.3b\n"); ide_register_hw(&hw, 1, &hwif); hwif->mmio = 2; hwif->OUTB = avila_ide_outb; hwif->OUTBSYNC = avila_ide_outbsync; hwif->OUTW = avila_ide_outw; hwif->OUTSW = avila_ide_outsw; hwif->INB = avila_ide_inb; hwif->INW = avila_ide_inw; hwif->INSW = avila_ide_insw; }
void __init sg8100_pci_init(void *sysdata) { gpio_line_config(INTA_PIN, IXP425_GPIO_IN | IXP425_GPIO_ACTIVE_LOW); gpio_line_isr_clear(INTA_PIN); ixp425_pci_init(sysdata); }