int
gpio_pin_list(gpio_handle_t handle, gpio_config_t **pcfgs)
{
int maxpins, i;
gpio_config_t *cfgs;
*pcfgs = NULL;
if (ioctl(handle, GPIOMAXPIN, &maxpins) < 0)
return (-1);
/* Reasonable values. */
if (maxpins < 0 || maxpins > 4096) {
errno = EINVAL;
return (-1);
}
cfgs = calloc(maxpins, sizeof(*cfgs));
if (cfgs == NULL)
return (-1);
for (i = 0; i <= maxpins; i++) {
cfgs[i].g_pin = i;
gpio_pin_config(handle, &cfgs[i]);
}
*pcfgs = cfgs;
return (maxpins);
}
static int gpio_sch_config(struct device *dev,
int access_op, u32_t pin, int flags)
{
const struct gpio_sch_config *info = dev->config->config_info;
/* Do some sanity check first */
if (flags & GPIO_INT) {
if (!(flags & GPIO_INT_EDGE)) {
/* controller does not support level trigger */
return -EINVAL;
}
}
if (access_op == GPIO_ACCESS_BY_PIN) {
if (pin >= info->bits) {
return -EINVAL;
}
gpio_pin_config(dev, pin, flags);
} else {
gpio_port_config(dev, flags);
}
return 0;
}
static inline void gpio_port_config(struct device *dev, int flags)
{
const struct gpio_sch_config *info = dev->config->config_info;
int pin;
for (pin = 0; pin < info->bits; pin++) {
gpio_pin_config(dev, pin, flags);
}
}
static int
gpio_pin_set_flag(gpio_handle_t handle, gpio_pin_t pin, uint32_t flag)
{
gpio_config_t cfg;
bzero(&cfg, sizeof(cfg));
cfg.g_pin = pin;
if (gpio_pin_config(handle, &cfg) < 0)
return (-1);
cfg.g_flags = flag;
return (gpio_pin_set_flags(handle, &cfg));
}
