/** * gpmi_set_timings - set GPMI timings * @pdev: pointer to GPMI platform device * @tm: pointer to structure &gpmi_nand_timing with new timings * * During initialization, GPMI uses safe sub-optimal timings, which * can be changed after reading boot control blocks */ void gpmi_set_timings(struct lba_data *data, struct gpmi_nand_timing *tm) { u32 period_ns = 1000000 / clk_get_rate(data->clk) + 1; u32 address_cycles, data_setup_cycles; u32 data_hold_cycles, data_sample_cycles; u32 busy_timeout; u32 t0, reg; address_cycles = gpmi_cycles_ceil(tm->address_setup, period_ns); data_setup_cycles = gpmi_cycles_ceil(tm->data_setup, period_ns); data_hold_cycles = gpmi_cycles_ceil(tm->data_hold, period_ns); data_sample_cycles = gpmi_cycles_ceil(tm->dsample_time + period_ns / 4, period_ns / 2); busy_timeout = gpmi_cycles_ceil(10000000 / 4096, period_ns); t0 = address_cycles << BP_GPMI_TIMING0_ADDRESS_SETUP; t0 |= data_setup_cycles << BP_GPMI_TIMING0_DATA_SETUP; t0 |= data_hold_cycles << BP_GPMI_TIMING0_DATA_HOLD; __raw_writel(t0, REGS_GPMI_BASE + HW_GPMI_TIMING0); __raw_writel(busy_timeout, REGS_GPMI_BASE + HW_GPMI_TIMING1); reg = __raw_readl(REGS_GPMI_BASE + HW_GPMI_CTRL1); #ifdef CONFIG_ARCH_STMP378X reg &= ~BM_GPMI_CTRL1_RDN_DELAY; reg |= data_sample_cycles << BP_GPMI_CTRL1_RDN_DELAY; #else reg &= ~BM_GPMI_CTRL1_DSAMPLE_TIME; reg |= data_sample_cycles << BP_GPMI_CTRL1_DSAMPLE_TIME; #endif __raw_writel(reg, REGS_GPMI_BASE + HW_GPMI_CTRL1); }
/** * gpmi_set_timings - set GPMI timings * @pdev: pointer to GPMI platform device * @tm: pointer to structure &gpmi_nand_timing with new timings * * During initialization, GPMI uses safe sub-optimal timings, which * can be changed after reading boot control blocks */ void gpmi_set_timings(struct lba_data *data, struct gpmi_nand_timing *tm) { u32 period_ns = 1000000 / clk_get_rate(data->clk) + 1; u32 address_cycles, data_setup_cycles; u32 data_hold_cycles, data_sample_cycles; u32 busy_timeout; u32 t0; address_cycles = gpmi_cycles_ceil(tm->address_setup, period_ns); data_setup_cycles = gpmi_cycles_ceil(tm->data_setup, period_ns); data_hold_cycles = gpmi_cycles_ceil(tm->data_hold, period_ns); data_sample_cycles = gpmi_cycles_ceil(tm->dsample_time + period_ns / 4, period_ns / 2); busy_timeout = gpmi_cycles_ceil(10000000 / 4096, period_ns); t0 = BF_GPMI_TIMING0_ADDRESS_SETUP(address_cycles) | BF_GPMI_TIMING0_DATA_SETUP(data_setup_cycles) | BF_GPMI_TIMING0_DATA_HOLD(data_hold_cycles); HW_GPMI_TIMING0_WR(t0); HW_GPMI_TIMING1_WR(BF_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT(busy_timeout)); #ifdef CONFIG_ARCH_STMP378X HW_GPMI_CTRL1_CLR(BM_GPMI_CTRL1_RDN_DELAY); HW_GPMI_CTRL1_SET(BF_GPMI_CTRL1_RDN_DELAY(data_sample_cycles)); #else HW_GPMI_CTRL1_CLR(BM_GPMI_CTRL1_DSAMPLE_TIME); HW_GPMI_CTRL1_SET(BF_GPMI_CTRL1_DSAMPLE_TIME(data_sample_cycles)); #endif }