static void gptm_write(void *opaque, target_phys_addr_t offset, uint64_t value, unsigned size) { gptm_state *s = (gptm_state *)opaque; uint32_t oldval; /* The timers should be disabled before changing the configuration. We take advantage of this and defer everything until the timer is enabled. */ switch (offset) { case 0x00: /* CFG */ s->config = value; break; case 0x04: /* TAMR */ s->mode[0] = value; break; case 0x08: /* TBMR */ s->mode[1] = value; break; case 0x0c: /* CTL */ oldval = s->control; s->control = value; /* TODO: Implement pause. */ if ((oldval ^ value) & 1) { if (value & 1) { gptm_reload(s, 0, 1); } else { gptm_stop(s, 0); } } if (((oldval ^ value) & 0x100) && s->config >= 4) { if (value & 0x100) { gptm_reload(s, 1, 1); } else { gptm_stop(s, 1); } } break; case 0x18: /* IMR */ s->mask = value & 0x77; gptm_update_irq(s); break; case 0x24: /* CR */ s->state &= ~value; break; case 0x28: /* TAILR */ s->load[0] = value & 0xffff; if (s->config < 4) { s->load[1] = value >> 16; } break; case 0x2c: /* TBILR */ s->load[1] = value & 0xffff; break; case 0x30: /* TAMARCHR */ s->match[0] = value & 0xffff; if (s->config < 4) { s->match[1] = value >> 16; }
static void gptm_tick(void *opaque) { gptm_state **p = (gptm_state **)opaque; gptm_state *s; int n; s = *p; n = p - s->opaque; if (s->config == 0) { s->state |= 1; if ((s->control & 0x20)) { /* Output trigger. */ qemu_irq_pulse(s->trigger); } if (s->mode[0] & 1) { /* One-shot. */ s->control &= ~1; } else { /* Periodic. */ gptm_reload(s, 0, 0); } } else if (s->config == 1) { /* RTC. */ uint32_t match; s->rtc++; match = s->match[0] | (s->match[1] << 16); if (s->rtc > match) s->rtc = 0; if (s->rtc == 0) { s->state |= 8; } gptm_reload(s, 0, 0); } else if (s->mode[n] == 0xa) { /* PWM mode. Not implemented. */ } else { qemu_log_mask(LOG_UNIMP, "GPTM: 16-bit timer mode unimplemented: 0x%x\n", s->mode[n]); } gptm_update_irq(s); }