int gpu_dvfs_calculate_env_data(struct kbase_device *kbdev)
{
	struct exynos_context *platform = (struct exynos_context *) kbdev->platform_context;
	static int polling_period = 0;

	DVFS_ASSERT(platform);

	gpu_dvfs_update_utilization(kbdev);

	polling_period -= platform->polling_speed;
	if (polling_period > 0)
		return 0;

	if (platform->dvs_is_enabled == true)
		return 0;

#ifdef MALI_SEC_HWCNT
	if (kbdev->hwcnt.is_hwcnt_attach == true && kbdev->hwcnt.is_hwcnt_enable == true
		&& kbdev->hwcnt.is_hwcnt_gpr_enable == false) {
		polling_period = platform->hwcnt_polling_speed;
		if (!gpu_control_is_power_on(kbdev))
			return 0;
		mutex_lock(&kbdev->hwcnt.mlock);
		if (kbdev->vendor_callbacks->hwcnt_update) {
			kbdev->vendor_callbacks->hwcnt_update(kbdev);
			dvfs_hwcnt_get_resource(kbdev);
			dvfs_hwcnt_utilization_equation(kbdev);
		}
		mutex_unlock(&kbdev->hwcnt.mlock);
	}
#endif

	return 0;
}
int gpu_dvfs_calculate_env_data(struct kbase_device *kbdev)
{
	struct exynos_context *platform = (struct exynos_context *) kbdev->platform_context;

	DVFS_ASSERT(platform);

	gpu_dvfs_update_utilization(kbdev);
	gpu_dvfs_update_hwc(kbdev);

	return 0;
}