int gpu_dvfs_governor_init(struct kbase_device *kbdev) { int governor_type = G3D_DVFS_GOVERNOR_DEFAULT; struct exynos_context *platform = (struct exynos_context *) kbdev->platform_context; DVFS_ASSERT(platform); #ifdef CONFIG_MALI_DVFS governor_type = platform->governor_type; #endif /* CONFIG_MALI_DVFS */ if (gpu_dvfs_governor_setting(platform, governor_type) < 0) { GPU_LOG(DVFS_WARNING, DUMMY, 0u, 0u, "%s: fail to initialize governor\n", __func__); return -1; } //share table_size among governors, as every single governor has same table_size. platform->save_cpu_max_freq = kmalloc(sizeof(int) * platform->table_size, GFP_KERNEL); gpu_dvfs_update_asv_table(platform); gpu_dvfs_decide_max_clock(platform); #if defined(CONFIG_MALI_DVFS) && defined(CONFIG_CPU_THERMAL_IPA) gpu_ipa_dvfs_calc_norm_utilisation(kbdev); #endif /* CONFIG_MALI_DVFS && CONFIG_CPU_THERMAL_IPA */ return 0; }
static void gpu_dvfs_update_utilization(struct kbase_device *kbdev) { unsigned long flags; struct exynos_context *platform = (struct exynos_context *) kbdev->platform_context; DVFS_ASSERT(platform); #if defined(CONFIG_MALI_DVFS) && defined(CONFIG_CPU_THERMAL_IPA) if (platform->time_tick < platform->gpu_dvfs_time_interval) { platform->time_tick++; platform->time_busy += kbdev->pm.metrics.time_busy; platform->time_idle += kbdev->pm.metrics.time_idle; } else { platform->time_busy = kbdev->pm.metrics.time_busy; platform->time_idle = kbdev->pm.metrics.time_idle; platform->time_tick = 0; } #endif /* CONFIG_MALI_DVFS && CONFIG_CPU_THERMAL_IPA */ spin_lock_irqsave(&platform->gpu_dvfs_spinlock, flags); #if SLSI_INTEGRATION /* Temporary patch */ platform->env_data.utilization = kbase_pm_get_dvfs_utilisation(kbdev, 0, 0); #else platform->env_data.utilization = kbase_platform_dvfs_event(kbdev, 0); #endif spin_unlock_irqrestore(&platform->gpu_dvfs_spinlock, flags); #if defined(CONFIG_MALI_DVFS) && defined(CONFIG_CPU_THERMAL_IPA) gpu_ipa_dvfs_calc_norm_utilisation(kbdev); #endif /* CONFIG_MALI_DVFS && CONFIG_CPU_THERMAL_IPA */ }
int kbase_platform_dvfs_event(struct kbase_device *kbdev, u32 utilisation) { #ifdef CONFIG_MALI_MIDGARD_DVFS unsigned long flags; #endif /* CONFIG_MALI_MIDGARD_DVFS */ struct exynos_context *platform = (struct exynos_context *) kbdev->platform_context; if (!platform) { GPU_LOG(DVFS_ERROR, "platform context is not initialized\n"); return -ENODEV; } #ifdef CONFIG_MALI_MIDGARD_DVFS spin_lock_irqsave(&platform->gpu_dvfs_spinlock, flags); #ifdef CONFIG_CPU_THERMAL_IPA if (platform->time_tick < GPU_DVFS_TIME_INTERVAL) { platform->time_tick++; platform->time_busy += kbdev->pm.metrics.time_busy; platform->time_idle += kbdev->pm.metrics.time_idle; } else { platform->time_busy = kbdev->pm.metrics.time_busy; platform->time_idle = kbdev->pm.metrics.time_idle; platform->time_tick = 0; } #endif /* CONFIG_CPU_THERMAL_IPA */ platform->utilization = utilisation; #ifdef CONFIG_CPU_THERMAL_IPA gpu_ipa_dvfs_calc_norm_utilisation(kbdev); #endif /* CONFIG_CPU_THERMAL_IPA */ spin_unlock_irqrestore(&platform->gpu_dvfs_spinlock, flags); #endif /* CONFIG_MALI_MIDGARD_DVFS */ #if defined(SLSI_INTEGRATION) && defined(CL_UTILIZATION_BOOST_BY_TIME_WEIGHT) atomic_set(&kbdev->pm.metrics.time_compute_jobs, 0); atomic_set(&kbdev->pm.metrics.time_vertex_jobs, 0); atomic_set(&kbdev->pm.metrics.time_fragment_jobs, 0); #endif if (platform->dvfs_wq) queue_work_on(0, platform->dvfs_wq, &gpu_dvfs_work); GPU_LOG(DVFS_DEBUG, "[G3D] dvfs hanlder is called\n"); return 0; }
int gpu_dvfs_governor_init(struct kbase_device *kbdev, int governor_type) { struct exynos_context *platform = (struct exynos_context *) kbdev->platform_context; DVFS_ASSERT(platform); if (gpu_dvfs_governor_setting(platform, governor_type) < 0) { GPU_LOG(DVFS_WARNING, DUMMY, 0u, 0u, "%s: fail to initialize governor\n", __func__); return -1; } gpu_dvfs_update_asv_table(platform); gpu_dvfs_decide_max_clock(platform); #if defined(CONFIG_MALI_DVFS) && defined(CONFIG_CPU_THERMAL_IPA) gpu_ipa_dvfs_calc_norm_utilisation(kbdev); #endif /* CONFIG_MALI_DVFS && CONFIG_CPU_THERMAL_IPA */ return 0; }
int gpu_dvfs_governor_init(struct kbase_device *kbdev, int governor_type) { unsigned long flags; #ifdef CONFIG_MALI_T6XX_DVFS int i, total = 0; #endif /* CONFIG_MALI_T6XX_DVFS */ struct exynos_context *platform = (struct exynos_context *) kbdev->platform_context; if (!platform) return -ENODEV; spin_lock_irqsave(&platform->gpu_dvfs_spinlock, flags); #ifdef CONFIG_MALI_T6XX_DVFS switch (governor_type) { case G3D_DVFS_GOVERNOR_DEFAULT: gpu_dvfs_get_next_freq = (GET_NEXT_FREQ)&gpu_dvfs_governor_default; platform->table = gpu_dvfs_infotbl_default; platform->table_size = GPU_DVFS_TABLE_SIZE(gpu_dvfs_infotbl_default); #if SOC_NAME == 5260 platform->devfreq_g3d_asv_abb = gpu_abb_infobl_default; #endif /* SOC_NAME */ platform->step = gpu_dvfs_get_level(platform, G3D_GOVERNOR_DEFAULT_CLOCK_DEFAULT); break; case G3D_DVFS_GOVERNOR_STATIC: gpu_dvfs_get_next_freq = (GET_NEXT_FREQ)&gpu_dvfs_governor_static; platform->table = gpu_dvfs_infotbl_default; platform->table_size = GPU_DVFS_TABLE_SIZE(gpu_dvfs_infotbl_default); #if SOC_NAME == 5260 platform->devfreq_g3d_asv_abb = gpu_abb_infobl_default; #endif /* SOC_NAME */ platform->step = gpu_dvfs_get_level(platform, G3D_GOVERNOR_DEFAULT_CLOCK_STATIC); break; case G3D_DVFS_GOVERNOR_BOOSTER: gpu_dvfs_get_next_freq = (GET_NEXT_FREQ)&gpu_dvfs_governor_booster; platform->table = gpu_dvfs_infotbl_default; platform->table_size = GPU_DVFS_TABLE_SIZE(gpu_dvfs_infotbl_default); #if SOC_NAME == 5260 platform->devfreq_g3d_asv_abb = gpu_abb_infobl_default; #endif /* SOC_NAME */ platform->step = gpu_dvfs_get_level(platform, G3D_GOVERNOR_DEFAULT_CLOCK_BOOSTER); break; default: GPU_LOG(DVFS_WARNING, "[gpu_dvfs_governor_init] invalid governor type\n"); gpu_dvfs_get_next_freq = (GET_NEXT_FREQ)&gpu_dvfs_governor_default; platform->table = gpu_dvfs_infotbl_default; platform->table_size = GPU_DVFS_TABLE_SIZE(gpu_dvfs_infotbl_default); #if SOC_NAME == 5260 platform->devfreq_g3d_asv_abb = gpu_abb_infobl_default; #endif /* SOC_NAME */ platform->step = gpu_dvfs_get_level(platform, G3D_GOVERNOR_DEFAULT_CLOCK_DEFAULT); break; } platform->utilization = 100; platform->target_lock_type = -1; platform->max_lock = 0; platform->min_lock = 0; #ifdef CONFIG_CPU_THERMAL_IPA gpu_ipa_dvfs_calc_norm_utilisation(kbdev); #endif /* CONFIG_CPU_THERMAL_IPA */ for (i = 0; i < NUMBER_LOCK; i++) { platform->user_max_lock[i] = 0; platform->user_min_lock[i] = 0; } platform->down_requirement = 1; platform->wakeup_lock = 0; platform->governor_type = governor_type; platform->governor_num = G3D_MAX_GOVERNOR_NUM; for (i = 0; i < G3D_MAX_GOVERNOR_NUM; i++) total += snprintf(platform->governor_list+total, sizeof(platform->governor_list), "[%d] %s\n", i, governor_list[i]); gpu_dvfs_init_time_in_state(platform); #else platform->table = gpu_dvfs_infotbl_default; platform->table_size = GPU_DVFS_TABLE_SIZE(gpu_dvfs_infotbl_default); #if SOC_NAME == 5260 platform->devfreq_g3d_asv_abb = gpu_abb_infobl_default; #endif /* SOC_NAME */ platform->step = gpu_dvfs_get_level(platform, MALI_DVFS_START_FREQ); #endif /* CONFIG_MALI_T6XX_DVFS */ platform->cur_clock = platform->table[platform->step].clock; /* asv info update */ gpu_dvfs_update_asv_table(platform, governor_type); spin_unlock_irqrestore(&platform->gpu_dvfs_spinlock, flags); return 1; }