static void create_ib1(struct adreno_context *drawctxt, unsigned int *cmd, unsigned int *start, unsigned int *end) { cmd[0] = PM4_HDR_INDIRECT_BUFFER_PFD; cmd[1] = gpuaddr(start, &drawctxt->gpustate); cmd[2] = end - start; }
/* quad for saving/restoring gmem */ static void build_quad_vtxbuff(struct adreno_context *drawctxt, struct tmp_ctx *ctx, struct gmem_shadow_t *shadow) { unsigned int *cmd = ctx->cmd; /* quad vertex buffer location (in GPU space) */ shadow->quad_vertices.hostptr = cmd; shadow->quad_vertices.gpuaddr = gpuaddr(cmd, &drawctxt->gpustate); cmd += QUAD_LEN; /* tex coord buffer location (in GPU space) */ shadow->quad_texcoords.hostptr = cmd; shadow->quad_texcoords.gpuaddr = gpuaddr(cmd, &drawctxt->gpustate); cmd += TEXCOORD_LEN; set_gmem_copy_quad(shadow); ctx->cmd = cmd; }
static void dump_float(float *dwords, uint32_t sizedwords, int level) { int i; for (i = 0; i < sizedwords; i++) { if ((i % 8) == 0) printf("%08x:%s", gpuaddr(dwords), levels[level]); else printf(" "); printf("%8f", *(dwords++)); if ((i % 8) == 7) printf("\n"); } if (i % 8) printf("\n"); }
/* chicken restore */ static unsigned int *build_chicken_restore_cmds( struct adreno_context *drawctxt, struct tmp_ctx *ctx) { unsigned int *start = ctx->cmd; unsigned int *cmds = start; *cmds++ = pm4_type3_packet(PM4_WAIT_FOR_IDLE, 1); *cmds++ = 0; *cmds++ = pm4_type0_packet(REG_TP0_CHICKEN, 1); ctx->chicken_restore = gpuaddr(cmds, &drawctxt->gpustate); *cmds++ = 0x00000000; /* create indirect buffer command for above command sequence */ create_ib1(drawctxt, drawctxt->chicken_restore, start, cmds); return cmds; }
static void build_shader_save_restore_cmds(struct adreno_context *drawctxt, struct tmp_ctx *ctx) { unsigned int *cmd = ctx->cmd; unsigned int *save, *restore, *fixup; #if defined(PM4_IM_STORE) unsigned int *startSizeVtx, *startSizePix, *startSizeShared; #endif unsigned int *partition1; unsigned int *shaderBases, *partition2; #if defined(PM4_IM_STORE) /* compute vertex, pixel and shared instruction shadow GPU addresses */ ctx->shader_vertex = drawctxt->gpustate.gpuaddr + SHADER_OFFSET; ctx->shader_pixel = ctx->shader_vertex + SHADER_SHADOW_SIZE; ctx->shader_shared = ctx->shader_pixel + SHADER_SHADOW_SIZE; #endif /* restore shader partitioning and instructions */ restore = cmd; /* start address */ /* Invalidate Vertex & Pixel instruction code address and sizes */ *cmd++ = pm4_type3_packet(PM4_INVALIDATE_STATE, 1); *cmd++ = 0x00000300; /* 0x100 = Vertex, 0x200 = Pixel */ /* Restore previous shader vertex & pixel instruction bases. */ *cmd++ = pm4_type3_packet(PM4_SET_SHADER_BASES, 1); shaderBases = cmd++; /* TBD #5: shader bases (from fixup) */ /* write the shader partition information to a scratch register */ *cmd++ = pm4_type0_packet(REG_SQ_INST_STORE_MANAGMENT, 1); partition1 = cmd++; /* TBD #4a: partition info (from save) */ #if defined(PM4_IM_STORE) /* load vertex shader instructions from the shadow. */ *cmd++ = pm4_type3_packet(PM4_IM_LOAD, 2); *cmd++ = ctx->shader_vertex + 0x0; /* 0x0 = Vertex */ startSizeVtx = cmd++; /* TBD #1: start/size (from save) */ /* load pixel shader instructions from the shadow. */ *cmd++ = pm4_type3_packet(PM4_IM_LOAD, 2); *cmd++ = ctx->shader_pixel + 0x1; /* 0x1 = Pixel */ startSizePix = cmd++; /* TBD #2: start/size (from save) */ /* load shared shader instructions from the shadow. */ *cmd++ = pm4_type3_packet(PM4_IM_LOAD, 2); *cmd++ = ctx->shader_shared + 0x2; /* 0x2 = Shared */ startSizeShared = cmd++; /* TBD #3: start/size (from save) */ #endif /* create indirect buffer command for above command sequence */ create_ib1(drawctxt, drawctxt->shader_restore, restore, cmd); /* * fixup SET_SHADER_BASES data * * since self-modifying PM4 code is being used here, a seperate * command buffer is used for this fixup operation, to ensure the * commands are not read by the PM4 engine before the data fields * have been written. */ fixup = cmd; /* start address */ /* write the shader partition information to a scratch register */ *cmd++ = pm4_type0_packet(REG_SCRATCH_REG2, 1); partition2 = cmd++; /* TBD #4b: partition info (from save) */ /* mask off unused bits, then OR with shader instruction memory size */ *cmd++ = pm4_type3_packet(PM4_REG_RMW, 3); *cmd++ = REG_SCRATCH_REG2; /* AND off invalid bits. */ *cmd++ = 0x0FFF0FFF; /* OR in instruction memory size */ *cmd++ = (unsigned int)((SHADER_INSTRUCT_LOG2 - 5U) << 29); /* write the computed value to the SET_SHADER_BASES data field */ *cmd++ = pm4_type3_packet(PM4_REG_TO_MEM, 2); *cmd++ = REG_SCRATCH_REG2; /* TBD #5: shader bases (to restore) */ *cmd++ = gpuaddr(shaderBases, &drawctxt->gpustate); /* create indirect buffer command for above command sequence */ create_ib1(drawctxt, drawctxt->shader_fixup, fixup, cmd); /* save shader partitioning and instructions */ save = cmd; /* start address */ *cmd++ = pm4_type3_packet(PM4_WAIT_FOR_IDLE, 1); *cmd++ = 0; /* fetch the SQ_INST_STORE_MANAGMENT register value, * store the value in the data fields of the SET_CONSTANT commands * above. */ *cmd++ = pm4_type3_packet(PM4_REG_TO_MEM, 2); *cmd++ = REG_SQ_INST_STORE_MANAGMENT; /* TBD #4a: partition info (to restore) */ *cmd++ = gpuaddr(partition1, &drawctxt->gpustate); *cmd++ = pm4_type3_packet(PM4_REG_TO_MEM, 2); *cmd++ = REG_SQ_INST_STORE_MANAGMENT; /* TBD #4b: partition info (to fixup) */ *cmd++ = gpuaddr(partition2, &drawctxt->gpustate); #if defined(PM4_IM_STORE) /* store the vertex shader instructions */ *cmd++ = pm4_type3_packet(PM4_IM_STORE, 2); *cmd++ = ctx->shader_vertex + 0x0; /* 0x0 = Vertex */ /* TBD #1: start/size (to restore) */ *cmd++ = gpuaddr(startSizeVtx, &drawctxt->gpustate); /* store the pixel shader instructions */ *cmd++ = pm4_type3_packet(PM4_IM_STORE, 2); *cmd++ = ctx->shader_pixel + 0x1; /* 0x1 = Pixel */ /* TBD #2: start/size (to restore) */ *cmd++ = gpuaddr(startSizePix, &drawctxt->gpustate); /* store the shared shader instructions if vertex base is nonzero */ *cmd++ = pm4_type3_packet(PM4_IM_STORE, 2); *cmd++ = ctx->shader_shared + 0x2; /* 0x2 = Shared */ /* TBD #3: start/size (to restore) */ *cmd++ = gpuaddr(startSizeShared, &drawctxt->gpustate); #endif *cmd++ = pm4_type3_packet(PM4_WAIT_FOR_IDLE, 1); *cmd++ = 0; /* create indirect buffer command for above command sequence */ create_ib1(drawctxt, drawctxt->shader_save, save, cmd); ctx->cmd = cmd; }
static void build_regrestore_cmds(struct adreno_device *adreno_dev, struct adreno_context *drawctxt, struct tmp_ctx *ctx) { unsigned int *start = ctx->cmd; unsigned int *cmd = start; unsigned int i = 0; unsigned int reg_array_size = 0; const unsigned int *ptr_register_ranges; *cmd++ = pm4_type3_packet(PM4_WAIT_FOR_IDLE, 1); *cmd++ = 0; /* H/W Registers */ /* deferred pm4_type3_packet(PM4_LOAD_CONSTANT_CONTEXT, ???); */ cmd++; #ifdef CONFIG_MSM_KGSL_DISABLE_SHADOW_WRITES /* Force mismatch */ *cmd++ = ((drawctxt->gpustate.gpuaddr + REG_OFFSET) & 0xFFFFE000) | 1; #else *cmd++ = (drawctxt->gpustate.gpuaddr + REG_OFFSET) & 0xFFFFE000; #endif /* Based on chip id choose the registers ranges*/ if (adreno_is_a220(adreno_dev)) { ptr_register_ranges = register_ranges_a22x; reg_array_size = ARRAY_SIZE(register_ranges_a22x); } else { ptr_register_ranges = register_ranges_a20x; reg_array_size = ARRAY_SIZE(register_ranges_a20x); } for (i = 0; i < (reg_array_size/2); i++) { cmd = reg_range(cmd, ptr_register_ranges[i*2], ptr_register_ranges[i*2+1]); } /* Now we know how many register blocks we have, we can compute command * length */ start[2] = pm4_type3_packet(PM4_LOAD_CONSTANT_CONTEXT, (cmd - start) - 3); /* Enable shadowing for the entire register block. */ #ifdef CONFIG_MSM_KGSL_DISABLE_SHADOW_WRITES start[4] |= (0 << 24) | (4 << 16); /* Disable shadowing. */ #else start[4] |= (1 << 24) | (4 << 16); #endif /* Need to handle some of the registers separately */ *cmd++ = pm4_type0_packet(REG_SQ_GPR_MANAGEMENT, 1); ctx->reg_values[0] = gpuaddr(cmd, &drawctxt->gpustate); *cmd++ = 0x00040400; *cmd++ = pm4_type3_packet(PM4_WAIT_FOR_IDLE, 1); *cmd++ = 0; *cmd++ = pm4_type0_packet(REG_TP0_CHICKEN, 1); ctx->reg_values[1] = gpuaddr(cmd, &drawctxt->gpustate); *cmd++ = 0x00000000; if (adreno_is_a220(adreno_dev)) { unsigned int i; unsigned int j = 2; for (i = REG_LEIA_VSC_BIN_SIZE; i <= REG_LEIA_VSC_PIPE_DATA_LENGTH_7; i++) { *cmd++ = pm4_type0_packet(i, 1); ctx->reg_values[j] = gpuaddr(cmd, &drawctxt->gpustate); *cmd++ = 0x00000000; j++; } } /* ALU Constants */ *cmd++ = pm4_type3_packet(PM4_LOAD_CONSTANT_CONTEXT, 3); *cmd++ = drawctxt->gpustate.gpuaddr & 0xFFFFE000; #ifdef CONFIG_MSM_KGSL_DISABLE_SHADOW_WRITES *cmd++ = (0 << 24) | (0 << 16) | 0; /* Disable shadowing */ #else *cmd++ = (1 << 24) | (0 << 16) | 0; #endif *cmd++ = ALU_CONSTANTS; /* Texture Constants */ *cmd++ = pm4_type3_packet(PM4_LOAD_CONSTANT_CONTEXT, 3); *cmd++ = (drawctxt->gpustate.gpuaddr + TEX_OFFSET) & 0xFFFFE000; #ifdef CONFIG_MSM_KGSL_DISABLE_SHADOW_WRITES /* Disable shadowing */ *cmd++ = (0 << 24) | (1 << 16) | 0; #else *cmd++ = (1 << 24) | (1 << 16) | 0; #endif *cmd++ = TEX_CONSTANTS; /* Boolean Constants */ *cmd++ = pm4_type3_packet(PM4_SET_CONSTANT, 1 + BOOL_CONSTANTS); *cmd++ = (2 << 16) | 0; /* the next BOOL_CONSTANT dwords is the shadow area for * boolean constants. */ ctx->bool_shadow = gpuaddr(cmd, &drawctxt->gpustate); cmd += BOOL_CONSTANTS; /* Loop Constants */ *cmd++ = pm4_type3_packet(PM4_SET_CONSTANT, 1 + LOOP_CONSTANTS); *cmd++ = (3 << 16) | 0; /* the next LOOP_CONSTANTS dwords is the shadow area for * loop constants. */ ctx->loop_shadow = gpuaddr(cmd, &drawctxt->gpustate); cmd += LOOP_CONSTANTS; /* create indirect buffer command for above command sequence */ create_ib1(drawctxt, drawctxt->reg_restore, start, cmd); ctx->cmd = cmd; }