static void puv3_load_kernel(const char *kernel_filename) { int size; if (kernel_filename == NULL && qtest_enabled()) { return; } if (kernel_filename == NULL) { error_report("kernel parameter cannot be empty"); exit(1); } /* only zImage format supported */ size = load_image_targphys(kernel_filename, KERNEL_LOAD_ADDR, KERNEL_MAX_SIZE); if (size < 0) { error_report("Load kernel error: '%s'", kernel_filename); exit(1); } /* cheat curses that we have a graphic console, only under ocd console */ graphic_console_init(NULL, 0, &no_ops, NULL); }
/* * FIXME/TODO: Kill this. * Temporary needed while DisplayState reorganization is in flight. */ void xen_init_display(int domid) { struct XenDevice *xfb, *xin; struct XenFB *fb; struct XenInput *in; int i = 0; wait_more: i++; main_loop_wait(10); /* miliseconds */ xfb = xen_be_find_xendev("vfb", domid, 0); xin = xen_be_find_xendev("vkbd", domid, 0); if (!xfb || !xin) { if (i < 256) goto wait_more; xen_be_printf(NULL, 1, "displaystate setup failed\n"); return; } /* vfb */ fb = container_of(xfb, struct XenFB, c.xendev); fb->c.ds = graphic_console_init(xenfb_update, xenfb_invalidate, NULL, NULL, fb); fb->have_console = 1; /* vkbd */ in = container_of(xin, struct XenInput, c.xendev); in->c.ds = fb->c.ds; /* retry ->init() */ xen_be_check_state(xin); xen_be_check_state(xfb); }
static int goldfish_fb_init(SysBusDevice *sbdev) { DeviceState *dev = DEVICE(sbdev); struct goldfish_fb_state *s = GOLDFISH_FB(dev); dev->id = g_strdup(TYPE_GOLDFISH_FB); sysbus_init_irq(sbdev, &s->irq); s->con = graphic_console_init(dev, 0, &goldfish_fb_ops, s); s->dpi = 165; /* TODO: Find better way to get actual value ! */ s->format = HAL_PIXEL_FORMAT_RGB_565; memory_region_init_io(&s->iomem, OBJECT(s), &goldfish_fb_iomem_ops, s, "goldfish_fb", 0x100); sysbus_init_mmio(sbdev, &s->iomem); register_savevm(dev, "goldfish_fb", 0, GOLDFISH_FB_SAVE_VERSION, goldfish_fb_save, goldfish_fb_load, s); return 0; }
static int tcx_init1(SysBusDevice *dev) { TCXState *s = FROM_SYSBUS(TCXState, dev); ram_addr_t vram_offset = 0; int size; uint8_t *vram_base; memory_region_init_ram(&s->vram_mem, "tcx.vram", s->vram_size * (1 + 4 + 4)); vmstate_register_ram_global(&s->vram_mem); vram_base = memory_region_get_ram_ptr(&s->vram_mem); /* 8-bit plane */ s->vram = vram_base; size = s->vram_size; memory_region_init_alias(&s->vram_8bit, "tcx.vram.8bit", &s->vram_mem, vram_offset, size); sysbus_init_mmio(dev, &s->vram_8bit); vram_offset += size; vram_base += size; /* DAC */ memory_region_init_io(&s->dac, &tcx_dac_ops, s, "tcx.dac", TCX_DAC_NREGS); sysbus_init_mmio(dev, &s->dac); /* TEC (dummy) */ memory_region_init_io(&s->tec, &dummy_ops, s, "tcx.tec", TCX_TEC_NREGS); sysbus_init_mmio(dev, &s->tec); /* THC: NetBSD writes here even with 8-bit display: dummy */ memory_region_init_io(&s->thc24, &dummy_ops, s, "tcx.thc24", TCX_THC_NREGS_24); sysbus_init_mmio(dev, &s->thc24); if (s->depth == 24) { /* 24-bit plane */ size = s->vram_size * 4; s->vram24 = (uint32_t *)vram_base; s->vram24_offset = vram_offset; memory_region_init_alias(&s->vram_24bit, "tcx.vram.24bit", &s->vram_mem, vram_offset, size); sysbus_init_mmio(dev, &s->vram_24bit); vram_offset += size; vram_base += size; /* Control plane */ size = s->vram_size * 4; s->cplane = (uint32_t *)vram_base; s->cplane_offset = vram_offset; memory_region_init_alias(&s->vram_cplane, "tcx.vram.cplane", &s->vram_mem, vram_offset, size); sysbus_init_mmio(dev, &s->vram_cplane); s->ds = graphic_console_init(tcx24_update_display, tcx24_invalidate_display, tcx24_screen_dump, NULL, s); } else { /* THC 8 bit (dummy) */ memory_region_init_io(&s->thc8, &dummy_ops, s, "tcx.thc8", TCX_THC_NREGS_8); sysbus_init_mmio(dev, &s->thc8); s->ds = graphic_console_init(tcx_update_display, tcx_invalidate_display, tcx_screen_dump, NULL, s); } qemu_console_resize(s->ds, s->width, s->height); return 0; }
static int tcx_init1(SysBusDevice *dev) { TCXState *s = FROM_SYSBUS(TCXState, dev); int io_memory, dummy_memory; ram_addr_t vram_offset; int size; uint8_t *vram_base; vram_offset = qemu_ram_alloc(NULL, "tcx.vram", s->vram_size * (1 + 4 + 4)); vram_base = qemu_get_ram_ptr(vram_offset); s->vram_offset = vram_offset; /* 8-bit plane */ s->vram = vram_base; size = s->vram_size; sysbus_init_mmio(dev, size, s->vram_offset); vram_offset += size; vram_base += size; /* DAC */ io_memory = cpu_register_io_memory(tcx_dac_read, tcx_dac_write, s, DEVICE_NATIVE_ENDIAN); sysbus_init_mmio(dev, TCX_DAC_NREGS, io_memory); /* TEC (dummy) */ dummy_memory = cpu_register_io_memory(tcx_dummy_read, tcx_dummy_write, s, DEVICE_NATIVE_ENDIAN); sysbus_init_mmio(dev, TCX_TEC_NREGS, dummy_memory); /* THC: NetBSD writes here even with 8-bit display: dummy */ sysbus_init_mmio(dev, TCX_THC_NREGS_24, dummy_memory); if (s->depth == 24) { /* 24-bit plane */ size = s->vram_size * 4; s->vram24 = (uint32_t *)vram_base; s->vram24_offset = vram_offset; sysbus_init_mmio(dev, size, vram_offset); vram_offset += size; vram_base += size; /* Control plane */ size = s->vram_size * 4; s->cplane = (uint32_t *)vram_base; s->cplane_offset = vram_offset; sysbus_init_mmio(dev, size, vram_offset); s->ds = graphic_console_init(tcx24_update_display, tcx24_invalidate_display, tcx24_screen_dump, NULL, s); } else { /* THC 8 bit (dummy) */ sysbus_init_mmio(dev, TCX_THC_NREGS_8, dummy_memory); s->ds = graphic_console_init(tcx_update_display, tcx_invalidate_display, tcx_screen_dump, NULL, s); } qemu_console_resize(s->ds, s->width, s->height); return 0; }
void tcx_init(target_phys_addr_t addr, int vram_size, int width, int height, int depth) { TCXState *s; int io_memory, dummy_memory; ram_addr_t vram_offset; int size; uint8_t *vram_base; vram_offset = qemu_ram_alloc(vram_size * (1 + 4 + 4)); vram_base = qemu_get_ram_ptr(vram_offset); s = qemu_mallocz(sizeof(TCXState)); s->addr = addr; s->vram_offset = vram_offset; s->width = width; s->height = height; s->depth = depth; // 8-bit plane s->vram = vram_base; size = vram_size; cpu_register_physical_memory(addr + 0x00800000ULL, size, vram_offset); vram_offset += size; vram_base += size; io_memory = cpu_register_io_memory(0, tcx_dac_read, tcx_dac_write, s); cpu_register_physical_memory(addr + 0x00200000ULL, TCX_DAC_NREGS, io_memory); dummy_memory = cpu_register_io_memory(0, tcx_dummy_read, tcx_dummy_write, s); cpu_register_physical_memory(addr + 0x00700000ULL, TCX_TEC_NREGS, dummy_memory); if (depth == 24) { // 24-bit plane size = vram_size * 4; s->vram24 = (uint32_t *)vram_base; s->vram24_offset = vram_offset; cpu_register_physical_memory(addr + 0x02000000ULL, size, vram_offset); vram_offset += size; vram_base += size; // Control plane size = vram_size * 4; s->cplane = (uint32_t *)vram_base; s->cplane_offset = vram_offset; cpu_register_physical_memory(addr + 0x0a000000ULL, size, vram_offset); s->ds = graphic_console_init(tcx24_update_display, tcx24_invalidate_display, tcx24_screen_dump, NULL, s); } else { cpu_register_physical_memory(addr + 0x00300000ULL, TCX_THC_NREGS_8, dummy_memory); s->ds = graphic_console_init(tcx_update_display, tcx_invalidate_display, tcx_screen_dump, NULL, s); } // NetBSD writes here even with 8-bit display cpu_register_physical_memory(addr + 0x00301000ULL, TCX_THC_NREGS_24, dummy_memory); register_savevm("tcx", addr, 4, tcx_save, tcx_load, s); qemu_register_reset(tcx_reset, s); tcx_reset(s); qemu_console_resize(s->ds, width, height); }
static int vigs_device_init(PCIDevice *dev) { VIGSState *s = DO_UPCAST(VIGSState, dev.pci_dev, dev); struct vigs_backend *backend = NULL; XSetErrorHandler(x_error_handler); XInitThreads(); vigs_display = XOpenDisplay(0); if (!vigs_display) { fprintf(stderr, "Cannot open X display\n"); exit(1); } vigs_render_queue = work_queue_create("render_queue"); vigs_log_init(); if (s->vram_size < 16 * 1024 * 1024) { VIGS_LOG_WARN("\"vram_size\" is too small, defaulting to 16mb"); s->vram_size = 16 * 1024 * 1024; } if (s->ram_size < 1 * 1024 * 1024) { VIGS_LOG_WARN("\"ram_size\" is too small, defaulting to 1mb"); s->ram_size = 1 * 1024 * 1024; } pci_config_set_interrupt_pin(dev->config, 1); memory_region_init_ram(&s->vram_bar, OBJECT(s), TYPE_VIGS_DEVICE ".vram", s->vram_size); memory_region_init_ram(&s->ram_bar, OBJECT(s), TYPE_VIGS_DEVICE ".ram", s->ram_size); memory_region_init_io(&s->io_bar, OBJECT(s), &vigs_io_ops, s, TYPE_VIGS_DEVICE ".io", VIGS_IO_SIZE); pci_register_bar(&s->dev.pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->vram_bar); pci_register_bar(&s->dev.pci_dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->ram_bar); pci_register_bar(&s->dev.pci_dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->io_bar); backend = vigs_gl_backend_create(vigs_display); if (!backend) { goto fail; } s->fenceman = vigs_fenceman_create(); s->fence_ack_bh = qemu_bh_new(vigs_fence_ack_bh, s); s->con = graphic_console_init(DEVICE(dev), 0, &vigs_hw_ops, s); if (!s->con) { goto fail; } s->server = vigs_server_create(memory_region_get_ram_ptr(&s->vram_bar), memory_region_get_ram_ptr(&s->ram_bar), &vigs_dpy_ops, s, backend, vigs_render_queue); if (!s->server) { goto fail; } vigs_wsi = s->dev.wsi = &s->server->wsi; VIGS_LOG_INFO("VIGS initialized"); VIGS_LOG_DEBUG("vram_size = %u", s->vram_size); VIGS_LOG_DEBUG("ram_size = %u", s->ram_size); return 0; fail: if (backend) { backend->destroy(backend); } if (s->fence_ack_bh) { qemu_bh_delete(s->fence_ack_bh); } if (s->fenceman) { vigs_fenceman_destroy(s->fenceman); } memory_region_destroy(&s->io_bar); memory_region_destroy(&s->ram_bar); memory_region_destroy(&s->vram_bar); vigs_log_cleanup(); return -1; }
static void tcx_realizefn(DeviceState *dev, Error **errp) { SysBusDevice *sbd = SYS_BUS_DEVICE(dev); TCXState *s = TCX(dev); ram_addr_t vram_offset = 0; int size, ret; uint8_t *vram_base; char *fcode_filename; memory_region_init_ram(&s->vram_mem, OBJECT(s), "tcx.vram", s->vram_size * (1 + 4 + 4), &error_abort); vmstate_register_ram_global(&s->vram_mem); vram_base = memory_region_get_ram_ptr(&s->vram_mem); /* FCode ROM */ vmstate_register_ram_global(&s->rom); fcode_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, TCX_ROM_FILE); if (fcode_filename) { ret = load_image_targphys(fcode_filename, s->prom_addr, FCODE_MAX_ROM_SIZE); if (ret < 0 || ret > FCODE_MAX_ROM_SIZE) { error_report("tcx: could not load prom '%s'", TCX_ROM_FILE); } } /* 8-bit plane */ s->vram = vram_base; size = s->vram_size; memory_region_init_alias(&s->vram_8bit, OBJECT(s), "tcx.vram.8bit", &s->vram_mem, vram_offset, size); sysbus_init_mmio(sbd, &s->vram_8bit); vram_offset += size; vram_base += size; if (s->depth == 24) { /* 24-bit plane */ size = s->vram_size * 4; s->vram24 = (uint32_t *)vram_base; s->vram24_offset = vram_offset; memory_region_init_alias(&s->vram_24bit, OBJECT(s), "tcx.vram.24bit", &s->vram_mem, vram_offset, size); sysbus_init_mmio(sbd, &s->vram_24bit); vram_offset += size; vram_base += size; /* Control plane */ size = s->vram_size * 4; s->cplane = (uint32_t *)vram_base; s->cplane_offset = vram_offset; memory_region_init_alias(&s->vram_cplane, OBJECT(s), "tcx.vram.cplane", &s->vram_mem, vram_offset, size); sysbus_init_mmio(sbd, &s->vram_cplane); s->con = graphic_console_init(DEVICE(dev), 0, &tcx24_ops, s); } else { /* THC 8 bit (dummy) */ memory_region_init_io(&s->thc8, OBJECT(s), &dummy_ops, s, "tcx.thc8", TCX_THC_NREGS_8); sysbus_init_mmio(sbd, &s->thc8); s->con = graphic_console_init(DEVICE(dev), 0, &tcx_ops, s); } qemu_console_resize(s->con, s->width, s->height); }