int i915lightup(unsigned int pphysbase, unsigned int piobase,
unsigned int pmmio, unsigned int pgfx)
{
static struct edid edid;
int index;
unsigned long temp;
mmio = (void *)pmmio;
addrport = piobase;
dataport = addrport + 4;
physbase = pphysbase;
graphics = pgfx;
printk(BIOS_SPEW,
"i915lightup: graphics %p mmio %p addrport %04x physbase %08x\n",
(void *)graphics, mmio, addrport, physbase);
globalstart = rdtscll();
decode_edid((unsigned char *)&x60_edid_data,
sizeof(x60_edid_data), &edid);
htotal = (edid.ha - 1) | ((edid.ha + edid.hbl - 1) << 16);
printk(BIOS_SPEW, "I915_WRITE(HTOTAL(pipe), %08x)\n", htotal);
hblank = (edid.ha - 1) | ((edid.ha + edid.hbl - 1) << 16);
printk(BIOS_SPEW, "I915_WRITE(HBLANK(pipe),0x%08x)\n", hblank);
hsync = (edid.ha + edid.hso - 1) |
((edid.ha + edid.hso + edid.hspw - 1) << 16);
printk(BIOS_SPEW, "I915_WRITE(HSYNC(pipe),0x%08x)\n", hsync);
vtotal = (edid.va - 1) | ((edid.va + edid.vbl - 1) << 16);
printk(BIOS_SPEW, "I915_WRITE(VTOTAL(pipe), %08x)\n", vtotal);
vblank = (edid.va - 1) | ((edid.va + edid.vbl - 1) << 16);
printk(BIOS_SPEW, "I915_WRITE(VBLANK(pipe),0x%08x)\n", vblank);
vsync = (edid.va + edid.vso - 1) |
((edid.va + edid.vso + edid.vspw - 1) << 16);
printk(BIOS_SPEW, "I915_WRITE(VSYNC(pipe),0x%08x)\n", vsync);
printk(BIOS_SPEW, "Table has %d elements\n", niodefs);
index = run(0);
printk(BIOS_SPEW, "Run returns %d\n", index);
verbose = 0;
/* GTT is the Global Translation Table for the graphics pipeline.
* It is used to translate graphics addresses to physical
* memory addresses. As in the CPU, GTTs map 4K pages.
* There are 32 bits per pixel, or 4 bytes,
* which means 1024 pixels per page.
* There are 4250 GTTs on Link:
* 2650 (X) * 1700 (Y) pixels / 1024 pixels per page.
* The setgtt function adds a further bit of flexibility:
* it allows you to set a range (the first two parameters) to point
* to a physical address (third parameter);the physical address is
* incremented by a count (fourth parameter) for each GTT in the
* range.
* Why do it this way? For ultrafast startup,
* we can point all the GTT entries to point to one page,
* and set that page to 0s:
* memset(physbase, 0, 4096);
* setgtt(0, 4250, physbase, 0);
* this takes about 2 ms, and is a win because zeroing
* the page takes a up to 200 ms. We will be exploiting this
* trick in a later rev of this code.
* This call sets the GTT to point to a linear range of pages
* starting at physbase.
*/
if (gtt_setup(pmmio)) {
printk(BIOS_ERR, "ERROR: GTT Setup Failed!!!\n");
return 0;
}
setgtt(0, 800 , physbase, 4096);
temp = READ32(PGETLB_CTL);
printk(BIOS_INFO, "GTT PGETLB_CTL register: 0x%lx\n", temp);
if (temp & 1)
printk(BIOS_INFO, "GTT Enabled\n");
else
printk(BIOS_ERR, "ERROR: GTT is still Disabled!!!\n");
printk(BIOS_SPEW, "memset %p to 0x00 for %d bytes\n",
(void *)graphics, FRAME_BUFFER_BYTES);
memset((void *)graphics, 0x00, FRAME_BUFFER_BYTES);
printk(BIOS_SPEW, "%ld microseconds\n", globalmicroseconds());
i915_init_done = 1;
return 0;
}
static int intel_gma_init(struct northbridge_intel_i945_config *conf,
unsigned int pphysbase, unsigned int piobase,
void *pmmio, unsigned int pgfx)
{
struct edid edid;
u8 edid_data[128];
unsigned long temp;
int hpolarity, vpolarity;
u32 candp1, candn;
u32 best_delta = 0xffffffff;
u32 target_frequency;
u32 pixel_p1 = 1;
u32 pixel_n = 1;
u32 pixel_m1 = 1;
u32 pixel_m2 = 1;
u32 hactive, vactive, right_border, bottom_border;
u32 vsync, hsync, vblank, hblank, hfront_porch, vfront_porch;
u32 i, j;
u32 uma_size;
u16 reg16;
printk(BIOS_SPEW,
"i915lightup: graphics %p mmio %p addrport %04x physbase %08x\n",
(void *)pgfx, pmmio, piobase, pphysbase);
intel_gmbus_read_edid(pmmio + GMBUS0, 3, 0x50, edid_data, 128);
decode_edid(edid_data, sizeof(edid_data), &edid);
hpolarity = (edid.phsync == '-');
vpolarity = (edid.pvsync == '-');
hactive = edid.x_resolution;
vactive = edid.y_resolution;
right_border = edid.hborder;
bottom_border = edid.vborder;
vblank = edid.vbl;
hblank = edid.hbl;
vsync = edid.vspw;
hsync = edid.hspw;
hfront_porch = edid.hso;
vfront_porch = edid.vso;
for (i = 0; i < 2; i++)
for (j = 0; j < 0x100; j++)
/* R=j, G=j, B=j. */
write32(pmmio + PALETTE(i) + 4 * j, 0x10101 * j);
write32(pmmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS
| (read32(pmmio + PCH_PP_CONTROL) & ~PANEL_UNLOCK_MASK));
write32(pmmio + MI_ARB_STATE, MI_ARB_C3_LP_WRITE_ENABLE | (1 << 27));
/* Clean registers. */
for (i = 0; i < 0x20; i += 4)
write32(pmmio + RENDER_RING_BASE + i, 0);
for (i = 0; i < 0x20; i += 4)
write32(pmmio + FENCE_REG_965_0 + i, 0);
write32(pmmio + PP_ON_DELAYS, 0);
write32(pmmio + PP_OFF_DELAYS, 0);
/* Disable VGA. */
write32(pmmio + VGACNTRL, VGA_DISP_DISABLE);
/* Disable pipes. */
write32(pmmio + PIPECONF(0), 0);
write32(pmmio + PIPECONF(1), 0);
/* Init PRB0. */
write32(pmmio + HWS_PGA, 0x352d2000);
write32(pmmio + PRB0_CTL, 0);
write32(pmmio + PRB0_HEAD, 0);
write32(pmmio + PRB0_TAIL, 0);
write32(pmmio + PRB0_START, 0);
write32(pmmio + PRB0_CTL, 0x0001f001);
write32(pmmio + D_STATE, DSTATE_PLL_D3_OFF
| DSTATE_GFX_CLOCK_GATING | DSTATE_DOT_CLOCK_GATING);
write32(pmmio + ECOSKPD, 0x00010000);
write32(pmmio + HWSTAM, 0xeffe);
write32(pmmio + PORT_HOTPLUG_EN, conf->gpu_hotplug);
write32(pmmio + INSTPM, 0x08000000 | INSTPM_AGPBUSY_DIS);
target_frequency = conf->gpu_lvds_is_dual_channel ? edid.pixel_clock
: (2 * edid.pixel_clock);
/* Find suitable divisors. */
for (candp1 = 1; candp1 <= 8; candp1++) {
for (candn = 5; candn <= 10; candn++) {
u32 cur_frequency;
u32 m; /* 77 - 131. */
u32 denom; /* 35 - 560. */
u32 current_delta;
denom = candn * candp1 * 7;
/* Doesnt overflow for up to
5000000 kHz = 5 GHz. */
m = (target_frequency * denom
+ BASE_FREQUENCY / 2) / BASE_FREQUENCY;
if (m < 77 || m > 131)
continue;
cur_frequency = (BASE_FREQUENCY * m) / denom;
if (target_frequency > cur_frequency)
current_delta = target_frequency - cur_frequency;
else
current_delta = cur_frequency - target_frequency;
if (best_delta > current_delta) {
best_delta = current_delta;
pixel_n = candn;
pixel_p1 = candp1;
pixel_m2 = ((m + 3) % 5) + 7;
pixel_m1 = (m - pixel_m2) / 5;
}
}
}
if (best_delta == 0xffffffff) {
printk (BIOS_ERR, "Couldn't find GFX clock divisors\n");
return -1;
}
printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n",
hactive, vactive);
printk(BIOS_DEBUG, "Borders %d x %d\n", right_border, bottom_border);
printk(BIOS_DEBUG, "Blank %d x %d\n", hblank, vblank);
printk(BIOS_DEBUG, "Sync %d x %d\n", hsync, vsync);
printk(BIOS_DEBUG, "Front porch %d x %d\n", hfront_porch, vfront_porch);
printk(BIOS_DEBUG, (conf->gpu_lvds_use_spread_spectrum_clock
? "Spread spectrum clock\n"
: "DREF clock\n"));
printk(BIOS_DEBUG, (conf->gpu_lvds_is_dual_channel
? "Dual channel\n"
: "Single channel\n"));
printk(BIOS_DEBUG, "Polarities %d, %d\n",
hpolarity, vpolarity);
printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n",
pixel_n, pixel_m1, pixel_m2, pixel_p1);
printk(BIOS_DEBUG, "Pixel clock %d kHz\n",
BASE_FREQUENCY * (5 * pixel_m1 + pixel_m2) / pixel_n
/ (pixel_p1 * 7));
#if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
write32(pmmio + PF_WIN_SZ(0), vactive | (hactive << 16));
write32(pmmio + PF_WIN_POS(0), 0);
write32(pmmio + PF_CTL(0),PF_ENABLE | PF_FILTER_MED_3x3);
write32(pmmio + PFIT_CONTROL, PFIT_ENABLE | (1 << PFIT_PIPE_SHIFT) | HORIZ_AUTO_SCALE | VERT_AUTO_SCALE);
#else
/* Disable panel fitter (we're in native resolution). */
write32(pmmio + PF_CTL(0), 0);
write32(pmmio + PF_WIN_SZ(0), 0);
write32(pmmio + PF_WIN_POS(0), 0);
write32(pmmio + PFIT_PGM_RATIOS, 0);
write32(pmmio + PFIT_CONTROL, 0);
#endif
mdelay(1);
write32(pmmio + DSPCNTR(0), DISPPLANE_BGRX888
| DISPPLANE_SEL_PIPE_B | DISPPLANE_GAMMA_ENABLE);
mdelay(1);
write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS
| (read32(pmmio + PP_CONTROL) & ~PANEL_UNLOCK_MASK));
write32(pmmio + FP0(1),
((pixel_n - 2) << 16)
| ((pixel_m1 - 2) << 8) | pixel_m2);
write32(pmmio + DPLL(1),
DPLL_VGA_MODE_DIS |
DPLL_VCO_ENABLE | DPLLB_MODE_LVDS
| (conf->gpu_lvds_is_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
: DPLLB_LVDS_P2_CLOCK_DIV_14)
| (conf->gpu_lvds_use_spread_spectrum_clock
? DPLL_INTEGRATED_CLOCK_VLV | DPLL_INTEGRATED_CRI_CLK_VLV
: 0)
| (pixel_p1 << 16)
| (pixel_p1));
mdelay(1);
write32(pmmio + DPLL(1),
DPLL_VGA_MODE_DIS |
DPLL_VCO_ENABLE | DPLLB_MODE_LVDS
| (conf->gpu_lvds_is_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
: DPLLB_LVDS_P2_CLOCK_DIV_14)
| ((conf->gpu_lvds_use_spread_spectrum_clock ? 3 : 0) << 13)
| (pixel_p1 << 16)
| (pixel_p1));
mdelay(1);
write32(pmmio + HTOTAL(1),
((hactive + right_border + hblank - 1) << 16)
| (hactive - 1));
write32(pmmio + HBLANK(1),
((hactive + right_border + hblank - 1) << 16)
| (hactive + right_border - 1));
write32(pmmio + HSYNC(1),
((hactive + right_border + hfront_porch + hsync - 1) << 16)
| (hactive + right_border + hfront_porch - 1));
write32(pmmio + VTOTAL(1), ((vactive + bottom_border + vblank - 1) << 16)
| (vactive - 1));
write32(pmmio + VBLANK(1), ((vactive + bottom_border + vblank - 1) << 16)
| (vactive + bottom_border - 1));
write32(pmmio + VSYNC(1),
(vactive + bottom_border + vfront_porch + vsync - 1)
| (vactive + bottom_border + vfront_porch - 1));
#if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
write32(pmmio + PIPESRC(1), (639 << 16) | 399);
#else
write32(pmmio + PIPESRC(1), ((hactive - 1) << 16) | (vactive - 1));
#endif
mdelay(1);
write32(pmmio + DSPSIZE(0), (hactive - 1) | ((vactive - 1) << 16));
write32(pmmio + DSPPOS(0), 0);
/* Backlight init. */
write32(pmmio + FW_BLC_SELF, FW_BLC_SELF_EN_MASK);
write32(pmmio + FW_BLC, 0x011d011a);
write32(pmmio + FW_BLC2, 0x00000102);
write32(pmmio + FW_BLC_SELF, FW_BLC_SELF_EN_MASK);
write32(pmmio + FW_BLC_SELF, 0x0001003f);
write32(pmmio + FW_BLC, 0x011d0109);
write32(pmmio + FW_BLC2, 0x00000102);
write32(pmmio + FW_BLC_SELF, FW_BLC_SELF_EN_MASK);
write32(pmmio + BLC_PWM_CTL, conf->gpu_backlight);
edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63;
write32(pmmio + DSPADDR(0), 0);
write32(pmmio + DSPSURF(0), 0);
write32(pmmio + DSPSTRIDE(0), edid.bytes_per_line);
write32(pmmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888
| DISPPLANE_SEL_PIPE_B | DISPPLANE_GAMMA_ENABLE);
mdelay(1);
write32(pmmio + PIPECONF(1), PIPECONF_ENABLE);
write32(pmmio + LVDS, LVDS_ON
| (hpolarity << 20) | (vpolarity << 21)
| (conf->gpu_lvds_is_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
| LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
| LVDS_CLOCK_A_POWERUP_ALL
| LVDS_PIPE(1));
write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_RESET);
mdelay(1);
write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS
| PANEL_POWER_ON | PANEL_POWER_RESET);
printk (BIOS_DEBUG, "waiting for panel powerup\n");
while (1) {
u32 reg32;
reg32 = read32(pmmio + PP_STATUS);
if ((reg32 & PP_SEQUENCE_MASK) == PP_SEQUENCE_NONE)
break;
}
printk (BIOS_DEBUG, "panel powered up\n");
write32(pmmio + PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET);
/* Clear interrupts. */
write32(pmmio + DEIIR, 0xffffffff);
write32(pmmio + SDEIIR, 0xffffffff);
write32(pmmio + IIR, 0xffffffff);
write32(pmmio + IMR, 0xffffffff);
write32(pmmio + EIR, 0xffffffff);
if (gtt_setup(pmmio)) {
printk(BIOS_ERR, "ERROR: GTT Setup Failed!!!\n");
return 0;
}
/* Setup GTT. */
reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), GGC);
uma_size = 0;
if (!(reg16 & 2)) {
reg16 >>= 4;
reg16 &= 7;
switch (reg16) {
case 1:
uma_size = 1024;
break;
case 3:
uma_size = 8192;
break;
}
printk(BIOS_DEBUG, "%dM UMA\n", uma_size >> 10);
}
static void intel_gma_init(const struct northbridge_intel_pineview_config *info,
struct device *vga, u8 *mmio, u8 *gtt, u32 physbase, u16 piobase)
{
int i;
u32 hactive, vactive;
u32 temp;
printk(BIOS_SPEW, "gtt %x mmio %x addrport %x physbase %x\n",
(u32)gtt, (u32)mmio, piobase, physbase);
gtt_setup(mmio);
pci_write_config16(vga, 0x52, 0x130);
/* Disable VGA. */
write32(mmio + VGACNTRL, VGA_DISP_DISABLE);
/* Disable pipes. */
write32(mmio + PIPECONF(0), 0);
write32(mmio + PIPECONF(1), 0);
write32(mmio + INSTPM, 0x800);
vga_gr_write(0x18, 0);
write32(mmio + VGA0, 0x200074);
write32(mmio + VGA1, 0x200074);
write32(mmio + DSPFW3, 0x7f3f00c1 & ~PINEVIEW_SELF_REFRESH_EN);
write32(mmio + DSPCLK_GATE_D, 0);
write32(mmio + FW_BLC, 0x03060106);
write32(mmio + FW_BLC2, 0x00000306);
write32(mmio + ADPA, ADPA_DAC_ENABLE
| ADPA_PIPE_A_SELECT
| ADPA_HOTPLUG_BITS
| ADPA_USE_VGA_HVPOLARITY
| ADPA_VSYNC_CNTL_ENABLE
| ADPA_HSYNC_CNTL_ENABLE
| ADPA_DPMS_ON
);
write32(mmio + 0x7041c, 0x0);
write32(mmio + DPLL_MD(0), 0x3);
write32(mmio + DPLL_MD(1), 0x3);
write32(mmio + DSPCNTR(1), 0x1000000);
write32(mmio + PIPESRC(1), 0x027f01df);
vga_misc_write(0x67);
const u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f,
0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00,
0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3,
0xff
};
vga_cr_write(0x11, 0);
for (i = 0; i <= 0x18; i++)
vga_cr_write(i, cr[i]);
// Disable screen memory to prevent garbage from appearing.
vga_sr_write(1, vga_sr_read(1) | 0x20);
hactive = 640;
vactive = 400;
mdelay(1);
write32(mmio + DPLL(0),
DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL
| DPLL_VGA_MODE_DIS
| DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
| 0x400601
);
mdelay(1);
write32(mmio + DPLL(0),
DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL
| DPLL_VGA_MODE_DIS
| DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
| 0x400601
);
write32(mmio + ADPA, ADPA_DAC_ENABLE
| ADPA_PIPE_A_SELECT
| ADPA_HOTPLUG_BITS
| ADPA_USE_VGA_HVPOLARITY
| ADPA_VSYNC_CNTL_ENABLE
| ADPA_HSYNC_CNTL_ENABLE
| ADPA_DPMS_ON
);
write32(mmio + HTOTAL(1), 0x031f027f);
write32(mmio + HBLANK(1), 0x03170287);
write32(mmio + HSYNC(1), 0x02ef028f);
write32(mmio + VTOTAL(1), 0x020c01df);
write32(mmio + VBLANK(1), 0x020401e7);
write32(mmio + VSYNC(1), 0x01eb01e9);
write32(mmio + HTOTAL(0),
((hactive - 1) << 16)
| (hactive - 1));
write32(mmio + HBLANK(0),
((hactive - 1) << 16)
| (hactive - 1));
write32(mmio + HSYNC(0),
((hactive - 1) << 16)
| (hactive - 1));
write32(mmio + VTOTAL(0), ((vactive - 1) << 16)
| (vactive - 1));
write32(mmio + VBLANK(0), ((vactive - 1) << 16)
| (vactive - 1));
write32(mmio + VSYNC(0),
((vactive - 1) << 16)
| (vactive - 1));
write32(mmio + PF_WIN_POS(0), 0);
write32(mmio + PIPESRC(0), (639 << 16) | 399);
write32(mmio + PF_CTL(0),PF_ENABLE | PF_FILTER_MED_3x3);
write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16));
write32(mmio + PFIT_CONTROL, 0x0);
mdelay(1);
write32(mmio + FDI_RX_CTL(0), 0x00002040);
mdelay(1);
write32(mmio + FDI_RX_CTL(0), 0x80002050);
write32(mmio + FDI_TX_CTL(0), 0x00044000);
mdelay(1);
write32(mmio + FDI_TX_CTL(0), 0x80044000);
write32(mmio + PIPECONF(0), PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN);
write32(mmio + VGACNTRL, 0x0);
write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888);
mdelay(1);
write32(mmio + ADPA, ADPA_DAC_ENABLE
| ADPA_PIPE_A_SELECT
| ADPA_HOTPLUG_BITS
| ADPA_USE_VGA_HVPOLARITY
| ADPA_VSYNC_CNTL_ENABLE
| ADPA_HSYNC_CNTL_ENABLE
| ADPA_DPMS_ON
);
write32(mmio + DSPFW3, 0x7f3f00c1);
write32(mmio + MI_MODE, 0x200 | VS_TIMER_DISPATCH);
write32(mmio + CACHE_MODE_0, (0x6820 | (1 << 9)) & ~(1 << 5));
write32(mmio + CACHE_MODE_1, 0x380 & ~(1 << 9));
for (i = 0; i < (8192 - 512) / 4; i++) {
outl((i << 2) | 1, piobase);
outl(physbase + (i << 12) + 1, piobase + 4);
}
temp = read32(mmio + PGETBL_CTL);
printk(BIOS_INFO, "GTT PGETBL_CTL register : 0x%08x\n", temp);
temp = read32(mmio + PGETBL2_CTL);
printk(BIOS_INFO, "GTT PGETBL2_CTL register: 0x%08x\n", temp);
/* Clear interrupts. */
write32(mmio + DEIIR, 0xffffffff);
write32(mmio + SDEIIR, 0xffffffff);
write32(mmio + IIR, 0xffffffff);
write32(mmio + IMR, 0xffffffff);
write32(mmio + EIR, 0xffffffff);
vga_textmode_init();
/* Enable screen memory. */
vga_sr_write(1, vga_sr_read(1) & ~0x20);
}
