void h8_register_write8(h83xx_state *h8, UINT32 address, UINT8 val)
{
UINT8 reg;
address &= 0xffffff;
reg = address & 0xff;
if(reg >= 0x60 && reg <= 0x9f)
{
h8_itu_write8(h8, reg, val);
}
switch (reg)
{
case 0xb3: // serial 0 send
h8->io->write_byte(H8_SERIAL_0, val);
h8_3002_InterruptRequest(h8, 54, 1);
h8_3002_InterruptRequest(h8, 55, 1);
break;
case 0xbb: // serial 1 send
h8->io->write_byte(H8_SERIAL_1, val);
h8_3002_InterruptRequest(h8, 58, 1);
h8_3002_InterruptRequest(h8, 59, 1);
break;
case 0xc7:
h8->io->write_byte(H8_PORT_4, val);
break;
case 0xcb: // port 6 data
h8->io->write_byte(H8_PORT_6, val);
break;
case 0xce: // port 7 data
h8->io->write_byte(H8_PORT_7, val);
break;
case 0xcf: // port 8 data
h8->io->write_byte(H8_PORT_8, val);
break;
case 0xd2: // port 9 data
h8->io->write_byte(H8_PORT_9, val);
break;
case 0xd3: // port a data
h8->io->write_byte(H8_PORT_A, val);
break;
case 0xd6: // port b data
h8->io->write_byte(H8_PORT_B, val);
break;
case 0xf6:
h8_ISR_w(h8, val);
break;
}
h8->per_regs[reg] = val;
}
static void h8itu_timer_expire(h83xx_state *h8, int which)
{
h8->timer[which]->adjust(attotime::never);
h8->h8TCNT[which] = 0;
h8->per_regs[tsr[which]] |= 4;
// interrupt on overflow ?
if(h8->per_regs[tier[which]] & 4)
{
h8_3002_InterruptRequest(h8, 26 + 4*which, 1);
}
}
static void h8itu_timer_4_cb(int num)
{
timer_adjust(h8.timer[4], TIME_NEVER, 0, 0);
h8.h8TCNT4 = 0;
h8.per_regs[TSR4] |= 4;
// interrupt on overflow ?
if(h8.per_regs[TIER4] & 4)
{
h8_3002_InterruptRequest(42);
}
}
static void h8itu_timer_3_cb(int num)
{
timer_adjust(h8.timer[3], TIME_NEVER, 0, 0);
h8.h8TCNT3 = 0;
h8.per_regs[TSR3] |= 4;
// interrupt on overflow ?
if(h8.per_regs[TIER3] & 4)
{
h8_3002_InterruptRequest(38);
}
}
static void h8itu_timer_0_cb(int num)
{
timer_adjust(h8.timer[0], TIME_NEVER, 0, 0);
h8.h8TCNT0 = 0;
h8.per_regs[TSR0] |= 4;
// interrupt on overflow ?
if(h8.per_regs[TIER0] & 4)
{
h8_3002_InterruptRequest(26);
}
}
static void h8itu_timer_2_cb(int num)
{
timer_adjust(h8.timer[2], TIME_NEVER, 0, 0);
h8.h8TCNT2 = 0;
h8.per_regs[TSR2] |= 4;
/* interrupt on overflow ? */
if(h8.per_regs[TIER2] & 4)
{
h8_3002_InterruptRequest(34);
}
}
static void h8itu_3007_timer_expire(h83xx_state *h8, int tnum)
{
int base = 0x68 + (tnum*8);
UINT16 count;
count = (h8->per_regs[base + 0x2]<<8) | h8->per_regs[base + 0x3];
count++;
//logerror("h8/3007 timer %d count = %04x\n",tnum,count);
// GRA match
if ((h8->per_regs[base + 0x1] & 0x03) && (count == ((h8->per_regs[base + 0x4]<<8) | h8->per_regs[base + 0x5])))
{
if ((h8->per_regs[base + 0x0] & 0x60) == 0x20)
{
//logerror("h8/3007 timer %d GRA match, restarting\n",tnum);
count = 0;
h8_3007_itu_refresh_timer(h8, tnum);
}
else
{
//logerror("h8/3007 timer %d GRA match, stopping\n",tnum);
h8->timer[tnum]->adjust(attotime::never);
}
h8->per_regs[0x64] |= 1<<tnum;
if(h8->per_regs[0x64] & (4<<tnum)) // interrupt enable
{
//logerror("h8/3007 timer %d GRA INTERRUPT\n",tnum);
h8_3002_InterruptRequest(h8, 24+tnum*4, 1);
}
}
// GRB match
if ((h8->per_regs[base + 0x1] & 0x30) && (count == ((h8->per_regs[base + 0x6]<<8) | h8->per_regs[base + 0x7])))
{
if ((h8->per_regs[base + 0x0] & 0x60) == 0x40)
{
//logerror("h8/3007 timer %d GRB match, restarting\n",tnum);
count = 0;
h8_3007_itu_refresh_timer(h8, tnum);
}
else
{
//logerror("h8/3007 timer %d GRB match, stopping\n",tnum);
h8->timer[tnum]->adjust(attotime::never);
}
h8->per_regs[0x65] |= 1<<tnum;
if(h8->per_regs[0x65] & (4<<tnum)) // interrupt enable
{
//logerror("h8/3007 timer %d GRB INTERRUPT\n",tnum);
h8_3002_InterruptRequest(h8, 25+tnum*4, 1);
}
}
// Overflow
if (((h8->per_regs[base + 0x1] & 0x33) == 0) && (count == 0))
{
//logerror("h8/3007 timer %d OVF match, restarting\n",tnum);
h8->per_regs[0x66] |= 1<<tnum;
if(h8->per_regs[0x66] & (4<<tnum)) // interrupt enable
{
//logerror("h8/3007 timer %d OVF INTERRUPT\n",tnum);
h8_3002_InterruptRequest(h8, 26+tnum*4, 1);
}
}
h8->per_regs[base + 0x2] = count >> 8;
h8->per_regs[base + 0x3] = count & 0xff;
}
