void drv_init_concerto(void)
{
RET_CODE ret;
const drvsvc_handle_t *p_public_drvsvc;
#ifndef WIN32
hal_otp_init();
#endif
/* DMA */
ret = hal_dma_init();
MT_ASSERT(ret == SUCCESS);
p_public_drvsvc = drv_public_svr_init();
MT_ASSERT(p_public_drvsvc != NULL);
ret = drv_dm_init();
MT_ASSERT(ret == SUCCESS);
ret = drv_i2c_init();
MT_ASSERT(ret == SUCCESS);
ret = drv_hdmi_init(p_public_drvsvc);
MT_ASSERT(ret == SUCCESS);
ret = drv_dmx_init();
MT_ASSERT(ret == SUCCESS);
ret = drv_video_init();
MT_ASSERT(ret == SUCCESS);
ret = drv_display_init();
MT_ASSERT(ret == SUCCESS);
mtos_task_sleep(1500);
OS_PRINTF("LOGO is NOT picture, assuming IFRAME.\n");
show_startup_iFram();
#if 0
ret = drv_gpe_init();
MT_ASSERT(ret == SUCCESS);
ret = drv_jpeg_init();
MT_ASSERT(ret == SUCCESS);
#endif
ret = uio_attach_concerto("concerto");
MT_ASSERT(ret == SUCCESS);
uio_init();
}
static void s_hal_spi_dma_init(hal_spi_t id, const hal_spi_cfg_t *cfg)
{
hal_spi_internal_item_t* intitem = s_hal_spi_theinternals.items[HAL_spi_id2index(id)];
hal_dma_cfg_t s_hal_spi_dma_cfg =
{
.transfer = hal_dma_transfer_mem2per, // it changes
.mode = hal_dma_mode_oneshot, // fixed
.intpriority = hal_int_priority06, // fixed
.datasize = cfg->sizeofframe, // fixed
.source = 0, // it changes
.destin = 0, // it changes
.cbk_on_transfer_done = NULL, // it changes
.arg_on_transfer_done = NULL // it changes
};
s_hal_spi_dma_cfg.transfer = hal_dma_transfer_per2mem;
s_hal_spi_dma_cfg.source = (void*)&s_hal_spi_stmSPImap[HAL_spi_id2index(id)]->DR;
s_hal_spi_dma_cfg.destin = intitem->dmarxframe;
s_hal_spi_dma_cfg.cbk_on_transfer_done = s_hal_spi_dma_on_tranfer_done_rx;
s_hal_spi_dma_cfg.arg_on_transfer_done = intitem;
hal_dma_init(s_hal_spi_dma_port2use_rx[HAL_spi_id2index(id)], &s_hal_spi_dma_cfg);
// init dma for tx
s_hal_spi_dma_cfg.transfer = hal_dma_transfer_mem2per;
// s_hal_spi_dma_cfg.source = intitem->dmatxframe;
// s_hal_spi_dma_cfg.destin = &s_hal_spi_stmSPImap[HAL_spi_id2index(id)]->DR;
s_hal_spi_dma_cfg.source = (void*)&s_hal_spi_stmSPImap[HAL_spi_id2index(id)]->DR;
s_hal_spi_dma_cfg.destin = intitem->dmatxframe;
s_hal_spi_dma_cfg.cbk_on_transfer_done = s_hal_spi_dma_on_tranfer_done_tx;
s_hal_spi_dma_cfg.arg_on_transfer_done = intitem;
hal_dma_init(s_hal_spi_dma_port2use_tx[HAL_spi_id2index(id)], &s_hal_spi_dma_cfg);
}
static void s_hal_spi_dma_on_tranfer_done_rx(void* p)
{
hal_spi_internal_item_t* intitem = (hal_spi_internal_item_t*)p;
// 1. copy the rx frame into fifo
if(hal_spi_dir_txonly != intitem->config.direction)
{
if(hal_true == hal_utility_fifo_full(&(intitem->fiforx)))
{
hal_utility_fifo_pop(&(intitem->fiforx));
}
hal_utility_fifo_put(&(intitem->fiforx), intitem->dmarxframe);
}
// 2. verify if we need to stop
hal_bool_t stopit = hal_false;
if(hal_spi_ownership_slave == intitem->config.ownership)
{
stopit = hal_false;
}
else if(hal_spi_ownership_master == intitem->config.ownership)
{
if(255 == intitem->frameburstcountdown)
{
stopit = hal_false;
}
else if(0 == intitem->frameburstcountdown)
{
stopit = hal_true;
}
else
{
intitem->frameburstcountdown --;
if(0 == intitem->frameburstcountdown)
{
stopit = hal_true;
}
else
{
stopit = hal_false;
}
}
}
if(hal_true == stopit)
{
// stop
}
else
{
if(hal_spi_dir_rxonly != intitem->config.direction)
{
// copy into txbuffer a new frame
if(hal_res_OK != hal_utility_fifo_get(&(intitem->fifotx), intitem->dmatxframe, NULL))
{ // put the dummy one.
memcpy(intitem->dmatxframe, intitem->dummytxframe, intitem->config.sizeofframe);
}
}
// retrigger tx
hal_dma_retrigger(s_hal_spi_dma_port2use_tx[HAL_spi_id2index(intitem->id)]);
// retrigger rx
hal_dma_retrigger(s_hal_spi_dma_port2use_rx[HAL_spi_id2index(intitem->id)]);
}
if(hal_spi_dir_txonly != intitem->config.direction)
{
// alert about a reception
hal_callback_t onframereceiv = intitem->config.onframereceiv;
if(NULL != onframereceiv)
{
onframereceiv(intitem->config.argonframereceiv);
}
}
}
