int application_start(int argc, char *argv[])
{
/* gpio port config */
led.port = GPIO_LED_IO;
/* set as output mode */
led.config = OUTPUT_PUSH_PULL;
/* configure GPIO with the given settings */
hal_gpio_init(&led);
/* gpio port config */
trigger.port = GPIO_TRIGGER_IO;
/* set as output mode */
trigger.config = OUTPUT_PUSH_PULL;
/* configure GPIO with the given settings */
hal_gpio_init(&trigger);
/* input pin config */
input.port = GPIO_INPUT_IO;
/* set as interrupt mode */
input.config = IRQ_MODE;
/* configure GPIO with the given settings */
hal_gpio_init(&input);
/* gpio interrupt config */
hal_gpio_enable_irq(&input, IRQ_TRIGGER_BOTH_EDGES, gpio_isr_handler, (void *) GPIO_INPUT_IO);
aos_post_delayed_action(1000, app_trigger_low_action, NULL);
aos_loop_run();
return 0;
}
void ssd1306_init(void)
{
oled_spi_dev.port = 1;
oled_spi_dev.config.mode = HAL_SPI_MODE_MASTER;
oled_spi_dev.config.freq = 6000000;
hal_spi_init(&oled_spi_dev);
//config reset and ds pin
gpio_oled_reset.port = 8; //PA8
gpio_oled_reset.config = OUTPUT_PUSH_PULL;
hal_gpio_init(&gpio_oled_reset);
hal_gpio_output_high(&gpio_oled_reset);
gpio_oled_cs.port = 22; //PA22
gpio_oled_cs.config = OUTPUT_PUSH_PULL;
hal_gpio_init(&gpio_oled_cs);
hal_gpio_output_high(&gpio_oled_cs);
aos_msleep(1);
hal_gpio_output_low(&gpio_oled_cs);
gpio_oled_ds.port = 20; //PA20
gpio_oled_ds.config = OUTPUT_PUSH_PULL;
hal_gpio_init(&gpio_oled_ds);
hal_gpio_output_high(&gpio_oled_ds);
aos_msleep(1);
hal_gpio_output_low(&gpio_oled_reset);
aos_msleep(1);
hal_gpio_output_high(&gpio_oled_reset);
//config oled
ssd1306_write(SSD1306_DISPLAYOFF, SSD1306_CMD);
ssd1306_write(SSD1306_SETDISPLAYCLOCKDIV, SSD1306_CMD);
ssd1306_write(80, SSD1306_CMD);
ssd1306_write(SSD1306_SETMULTIPLEX, SSD1306_CMD);
ssd1306_write(0x3F, SSD1306_CMD);
ssd1306_write(SSD1306_SETDISPLAYOFFSET, SSD1306_CMD);
ssd1306_write(0x00, SSD1306_CMD);
ssd1306_write(SSD1306_SETSTARTLINE, SSD1306_CMD);
ssd1306_write(SSD1306_ENABLE_CHARGE_PUMP, SSD1306_CMD);
ssd1306_write(0x14, SSD1306_CMD);
ssd1306_write(SSD1306_MEMORYMODE, SSD1306_CMD);
ssd1306_write(0x02, SSD1306_CMD);
ssd1306_write(0xA1, SSD1306_CMD);
ssd1306_write(SSD1306_COMSCANINC, SSD1306_CMD);
ssd1306_write(SSD1306_SETCOMPINS, SSD1306_CMD);
ssd1306_write(0X12, SSD1306_CMD);
ssd1306_write(SSD1306_SETCONTRAST, SSD1306_CMD);
ssd1306_write(0x1F, SSD1306_CMD); //set brightness
ssd1306_write(SSD1306_SETPRECHARGE, SSD1306_CMD);
ssd1306_write(0xF1, SSD1306_CMD);
ssd1306_write(SSD1306_SETVCOMDETECT, SSD1306_CMD);
ssd1306_write(0x30, SSD1306_CMD);
ssd1306_write(SSD1306_DISPLAYALLON_RESUME, SSD1306_CMD);
ssd1306_write(SSD1306_NORMALDISPLAY, SSD1306_CMD);
ssd1306_write(SSD1306_DISPLAYON, SSD1306_CMD);
return 0;
}
__externC void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR
hal_system_init( void )
{
#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_SRAM)
hal_wdog_disable();
hal_gpio_init();
hal_start_clocks();
#endif
#if defined(CYG_HAL_STARTUP_SRAM) && !defined(CYGHWR_HAL_CORTEXM_KINETIS_SRAM_UNIFIED)
// Note: For CYG_HAL_STARTUP_SRAM, the SRAM_L bank simulates ROM
// Relocate data from ROM to RAM
{
register cyg_uint32 *ram_p, *rom_p;
for( ram_p = &__ram_data_start, rom_p = &__rom_data_start;
ram_p < &__ram_data_end;
ram_p++, rom_p++ )
*ram_p = *rom_p;
}
// Relocate data from ROM to SRAM
{
register cyg_uint32 *ram_p, *sram_p;
for( ram_p = &__sram_data_start, sram_p = &__srom_data_start;
ram_p < &__sram_data_end;
ram_p++, sram_p++ )
*ram_p = *sram_p;
}
#endif
}
void board_init(void)
{
gpio_key_boot.port = KEY_BOOT;
gpio_key_boot.config = INPUT_PULL_UP;
hal_gpio_init(&gpio_key_boot);
hal_gpio_clear_irq(&gpio_key_boot);
hal_gpio_enable_irq(&gpio_key_boot, IRQ_TRIGGER_FALLING_EDGE, handle_elink_key, NULL);
gpio_key_ps.port = KEY_PS;
gpio_key_ps.config = INPUT_PULL_UP;
hal_gpio_init(&gpio_key_ps);
hal_gpio_clear_irq(&gpio_key_ps);
hal_gpio_enable_irq(&gpio_key_ps, IRQ_TRIGGER_FALLING_EDGE, handle_ps_key, NULL);
}
extern hal_result_t hal_led_init(hal_led_t id, const hal_led_cfg_t *cfg)
{
const hal_gpio_map_t *gm = NULL;
hal_result_t res = hal_res_NOK_generic;
if(hal_false == s_hal_led_supported_is(id))
{
return(hal_res_NOK_generic);
}
if(hal_true == s_hal_led_initted_is(id))
{
return(hal_res_OK);
}
gm = &hal_led__theboardconfig.gpiomap[HAL_led_id2index(id)].led;
// much better to init w/ hal_gpio_init() and not with hl_gpio_init() so that we fill the data structure of the gpio in hal.
res = hal_gpio_init(gm->gpio, &s_hal_led_gpio_config);
if(hal_res_OK != res)
{
return(res);
}
s_hal_led_initted_set(id);
// hal_led_off() must be after s_hal_led_initted_set();
hal_led_off(id);
return(hal_res_OK);
}
static hal_result_t s_hal_device_cantransceiver_simple_init(hal_cantransceiver_t id, void* initpar)
{
initpar = initpar;
const hal_gpio_map_t* map = &s_hal_device_cantransceiver__gpiomapof_enable[(uint8_t)id];
hal_gpio_init(map->gpio, &map->config);
s_hal_device_cantransceiver_simple_disable(id);
return(hal_res_OK);
}
/**
* gpio init in
*
* Initializes the specified pin as an input
*
* @param pin Pin number to set as input
* @param pull pull type
*
* @return int 0: no error; -1 otherwise.
*/
int
gpio_init_in(int pin, enum gpio_pull pull)
{
GPIO_InitTypeDef init_cfg;
init_cfg.GPIO_Mode = GPIO_Mode_IN;
init_cfg.GPIO_Speed = GPIO_Speed_Level_2;
init_cfg.GPIO_OType = GPIO_OType_PP;
init_cfg.GPIO_PuPd = hal_gpio_pull_to_cfg(pull);
return hal_gpio_init(pin, &init_cfg);
}
/**
* gpio init af
*
* Configure the specified pin for AF.
*/
int
hal_gpio_init_af(int pin, uint8_t af_type, enum gpio_pull pull)
{
GPIO_InitTypeDef gpio;
gpio.Mode = GPIO_MODE_AF_PP;
gpio.Speed = GPIO_SPEED_HIGH;
gpio.Pull = pull;
gpio.Alternate = af_type;
return hal_gpio_init(pin, &gpio);
}
/**
* gpio init in
*
* Initializes the specified pin as an input
*
* @param pin Pin number to set as input
* @param pull pull type
*
* @return int 0: no error; -1 otherwise.
*/
int
gpio_init_in(int pin, gpio_pull_t pull)
{
int rc;
GPIO_InitTypeDef init_cfg;
init_cfg.Mode = GPIO_MODE_INPUT;
init_cfg.Pull = pull;
rc = hal_gpio_init(pin, &init_cfg);
return rc;
}
/**
* gpio init out
*
* Initialize the specified pin as an output, setting the pin to the specified
* value.
*
* @param pin Pin number to set as output
* @param val Value to set pin
*
* @return int 0: no error; -1 otherwise.
*/
int
gpio_init_out(int pin, int val)
{
GPIO_InitTypeDef init_cfg;
init_cfg.GPIO_Mode = GPIO_Mode_OUT;
init_cfg.GPIO_Speed = GPIO_Speed_Level_2;
init_cfg.GPIO_OType = GPIO_OType_PP;
init_cfg.GPIO_PuPd = GPIO_PuPd_NOPULL;
return hal_gpio_init(pin, &init_cfg);
}
/**
* gpio init out
*
* Initialize the specified pin as an output, setting the pin to the specified
* value.
*
* @param pin Pin number to set as output
* @param val Value to set pin
*
* @return int 0: no error; -1 otherwise.
*/
int gpio_init_out(int pin, int val)
{
int rc;
GPIO_InitTypeDef init_cfg;
init_cfg.Mode = GPIO_MODE_OUTPUT_PP;
init_cfg.Pull = GPIO_NOPULL;
init_cfg.Speed = GPIO_SPEED_HIGH;
init_cfg.Alternate = 0;
rc = hal_gpio_init(pin, &init_cfg);
return rc;
}
static void brd_peri_init(void)
{
int i;
int gpcfg_num = sizeof(brd_gpio_table) / sizeof(brd_gpio_table[0]);
for (i = 0; i < gpcfg_num; ++i) {
hal_gpio_init(&brd_gpio_table[i]);
}
hal_i2c_init(&brd_i2c1_dev);
hal_i2c_init(&brd_i2c2_dev);
}
/**
* gpio init af
*
* Configure the specified pin for AF.
*/
int
hal_gpio_init_af(int pin, uint8_t af_type, enum gpio_pull pull)
{
GPIO_InitTypeDef gpio;
int rc;
gpio.GPIO_Mode = GPIO_Mode_AF;
gpio.GPIO_Speed = GPIO_Speed_Level_2;
gpio.GPIO_OType = GPIO_OType_PP;
gpio.GPIO_PuPd = hal_gpio_pull_to_cfg(pull);
rc = hal_gpio_init(pin, &gpio);
if (rc == 0) {
GPIO_PinAFConfig(portmap[GPIO_PORT(pin)], GPIO_INDEX(pin), af_type);
rc = 0;
}
return rc;
}
__externC void
hal_system_init(void)
{
#if defined(CYG_HAL_STARTUP_ROM) | defined(CYG_HAL_STARTUP_SRAM)
hal_gpio_init();
#endif
#if defined(CYG_HAL_STARTUP_ROM)
{
// Set flash accelerator according to CPU clock speed.
cyg_uint32 regval;
HAL_READ_UINT32(CYGHWR_HAL_LPC17XX_REG_SCB_BASE +
CYGHWR_HAL_LPC17XX_REG_FLASHCFG, regval);
regval &= ~CYGHWR_HAL_LPC17XX_REG_FLTIM_MASK;
regval |= CYGHWR_HAL_LPC17XX_REG_FLASHTIM;
HAL_WRITE_UINT32(CYGHWR_HAL_LPC17XX_REG_SCB_BASE +
CYGHWR_HAL_LPC17XX_REG_FLASHCFG, regval);
}
#endif
}
static void s_hal_brdcfg_mc4plus_vaux_5v0_init(void)
{
#if !defined(NNNEW)
static uint8_t initted = 0;
if(1 == initted)
{
return;
}
#else
if(1 == vaux_5v0_initted)
{
return;
}
#endif
hal_gpio_init(s_hal_brdcfg_mc4plus_vaux_5v0_gpiomap.gpio, &s_hal_brdcfg_mc4plus_vaux_5v0_gpiocfg);
#if !defined(NNNEW)
initted = 1;
#else
vaux_5v0_initted = 1;
#endif
s_hal_brdcfg_mc4plus_vaux_5v0_on();
}
extern hal_result_t hal_led_init(hal_led_t led, const hal_led_cfg_t *cfg)
{
const hal_gpio_cfg_t *gc = NULL;
hal_result_t res = hal_res_NOK_generic;
if(hal_false == s_hal_led_supported_is(led))
{
return(hal_res_NOK_generic);
}
gc = &hal_brdcfg_led__cfg[HAL_led_t2index(led)];
res = hal_gpio_init(gc->port, gc->pin, gc->dir, gc->speed);
if(hal_res_OK != res)
{
return(res);
}
s_hal_led_initted_set(led);
return(hal_res_OK);
}
extern hal_result_t hal_5v_init(const hal_5v_cfg_t *cfg)
{
hal_5v_theinternals_t* intitem = &s_hal_5v_theinternals;
if(hal_false == s_hal_5v_supported_is())
{
return(hal_res_NOK_generic);
}
if(NULL == cfg)
{
cfg = &hal_5v_cfg_default;
}
if(hal_true == s_hal_5v_initted_is())
{
if(0 == memcmp(cfg, &intitem->config, sizeof(hal_5v_cfg_t)))
{ // ok only if the previously used config is the same as the current one
return(hal_res_OK);
}
else
{
return(hal_res_NOK_generic);
}
}
// set config
memcpy(&intitem->config, cfg, sizeof(hal_5v_cfg_t));
// ok, now i init
hal_gpio_init(hal_5v__theboardconfig.gpiomap.gpio, &hal_5v__theboardconfig.gpiocfg);
s_hal_5v_initted_set();
return(hal_res_OK);
}
extern hal_result_t hal_led_init(hal_led_t id, const hal_led_cfg_t *cfg)
{
const hal_gpio_maP_t *gm = NULL;
hal_result_t res = hal_res_NOK_generic;
if(hal_false == s_hal_device_led_supported_is(id))
{
return(hal_res_NOK_generic);
}
gm = &hal_brdcfg_device_led__theconfig.gpiomap[HAL_device_led_id2index(id)].led;
res = hal_gpio_init(gm->gpio, &s_hal_led_gpio_config);
if(hal_res_OK != res)
{
return(res);
}
hal_gpio_setval(gm->gpio, hal_brdcfg_device_led__theconfig.value_off);
s_hal_device_led_initted_set(id);
return(hal_res_OK);
}
static void s_hal_spi_hw_gpio_init(hal_spi_t id, hal_spi_ownership_t ownership)
{
#if defined(HAL_USE_CPU_FAM_STM32F1)
static const GPIO_InitTypeDef s_hal_spi_sckmosi_master_altcfg =
{
.GPIO_Pin = 0,
.GPIO_Speed = GPIO_Speed_50MHz,
.GPIO_Mode = GPIO_Mode_AF_PP, // il PP serve per spi del display3 .... GPIO_Mode_AF_OD,
};
static const GPIO_InitTypeDef s_hal_spi_miso_master_altcfg =
{
.GPIO_Pin = 0,
.GPIO_Speed = GPIO_Speed_50MHz,
.GPIO_Mode = GPIO_Mode_IN_FLOATING, //GPIO_Mode_IPD, // oppure ... GPIO_Mode_IN_FLOATING?
};
static const GPIO_InitTypeDef s_hal_spi_sckmosi_slave_altcfg =
{
.GPIO_Pin = 0,
.GPIO_Speed = GPIO_Speed_50MHz,
.GPIO_Mode = GPIO_Mode_IN_FLOATING, //GPIO_Mode_IPD, // oppure ... GPIO_Mode_IN_FLOATING,
};
static const GPIO_InitTypeDef s_hal_spi_miso_slave_altcfg =
{
.GPIO_Pin = 0,
.GPIO_Speed = GPIO_Speed_50MHz,
.GPIO_Mode = GPIO_Mode_AF_PP,
};
// 1. prepare af.
// for spi1 (sck, miso, mosi): no-remap if it is (PA5, PA6, PA7). GPIO_Remap_SPI1 if it is (PB3, PB4, PB5).
// for spi2 (sck, miso, mosi): no remap if it is (PB13, PB14, PB15).
// for spi3 (sck, miso, mosi): no-remap if it is (PB3, PB4, PB5). GPIO_Remap_SPI3 if it is (PC10, PC11, PC12).
uint32_t afname = HAL_GPIO_AFNAME_NONE;
uint32_t afmode = HAL_GPIO_AFMODE_NONE;
hal_bool_t found = hal_false;
hal_gpio_port_t portsck = hal_brdcfg_spi__theconfig.gpio_sck[HAL_spi_id2index(id)].gpio.port;
hal_gpio_pin_t pinsck = hal_brdcfg_spi__theconfig.gpio_sck[HAL_spi_id2index(id)].gpio.pin;
hal_gpio_port_t portmiso = hal_brdcfg_spi__theconfig.gpio_miso[HAL_spi_id2index(id)].gpio.port;
hal_gpio_pin_t pinmiso = hal_brdcfg_spi__theconfig.gpio_miso[HAL_spi_id2index(id)].gpio.pin;
hal_gpio_port_t portmosi = hal_brdcfg_spi__theconfig.gpio_mosi[HAL_spi_id2index(id)].gpio.port;
hal_gpio_pin_t pinmosi = hal_brdcfg_spi__theconfig.gpio_mosi[HAL_spi_id2index(id)].gpio.pin;
if(hal_spi1 == id)
{
if((hal_gpio_portA == portsck) && (hal_gpio_pin5 == pinsck) && (hal_gpio_portA == portmiso) && (hal_gpio_pin6 == pinmiso) && (hal_gpio_portA == portmosi) && (hal_gpio_pin7 == pinmosi))
{ // PA5, PA6, PA7
afname = HAL_GPIO_AFNAME_NONE;
afmode = HAL_GPIO_AFMODE_NONE;
found = hal_true;
}
else if((hal_gpio_portB == portsck) && (hal_gpio_pin3 == pinsck) && (hal_gpio_portB == portmiso) && (hal_gpio_pin4 == pinmiso) && (hal_gpio_portB == portmosi) && (hal_gpio_pin5 == pinmosi))
{ // PB3, PB4, PB5
afname = GPIO_Remap_SPI1;
afmode = ENABLE;
found = hal_true;
}
}
else if(hal_spi2 == id)
{
if((hal_gpio_portB == portmiso) && (hal_gpio_portB == portmosi) && (hal_gpio_portB == portsck) && (hal_gpio_pin14 == pinmiso) && (hal_gpio_pin15 == pinmosi) && (hal_gpio_pin13 == pinsck))
{ // PB13, PB14, PB15
afname = HAL_GPIO_AFNAME_NONE;
afmode = HAL_GPIO_AFMODE_NONE;
found = hal_true;
}
}
else if(hal_spi3 == id)
{
if((hal_gpio_portB == portsck) && (hal_gpio_pin3 == pinsck) && (hal_gpio_portB == portmiso) && (hal_gpio_pin4 == pinmiso) && (hal_gpio_portB == portmosi) && (hal_gpio_pin5 == pinmosi))
{ // PB3, PB4, PB5
afname = HAL_GPIO_AFNAME_NONE;
afmode = HAL_GPIO_AFMODE_NONE;
found = hal_true;
}
else if((hal_gpio_portC == portsck) && (hal_gpio_pin10 == pinsck) && (hal_gpio_portC == portmiso) && (hal_gpio_pin11 == pinmiso) && (hal_gpio_portC == portmosi) && (hal_gpio_pin12 == pinmosi))
{ // PC10, PC11, PC12
afname = GPIO_Remap_SPI3;
afmode = ENABLE;
found = hal_true;
}
}
if(hal_false == found)
{
hal_base_on_fatalerror(hal_fatalerror_incorrectparameter, "hal_spi_init(): incorrect pin mapping");
}
hal_gpio_altcfg_t hal_spi_sck_altcfg;
hal_gpio_altcfg_t hal_spi_miso_altcfg;
hal_gpio_altcfg_t hal_spi_mosi_altcfg;
hal_gpio_cfg_t config;
// prepare the altcfg for sck, miso, mosi pins
if(hal_spi_ownership_master == ownership)
{
memcpy(&hal_spi_sck_altcfg, &s_hal_spi_sckmosi_master_altcfg, sizeof(hal_gpio_altcfg_t));
memcpy(&hal_spi_miso_altcfg, &s_hal_spi_miso_master_altcfg, sizeof(hal_gpio_altcfg_t));
memcpy(&hal_spi_mosi_altcfg, &s_hal_spi_sckmosi_master_altcfg, sizeof(hal_gpio_altcfg_t));
}
else
{
memcpy(&hal_spi_sck_altcfg, &s_hal_spi_sckmosi_slave_altcfg, sizeof(hal_gpio_altcfg_t));
memcpy(&hal_spi_miso_altcfg, &s_hal_spi_miso_slave_altcfg, sizeof(hal_gpio_altcfg_t));
memcpy(&hal_spi_mosi_altcfg, &s_hal_spi_sckmosi_slave_altcfg, sizeof(hal_gpio_altcfg_t));
}
hal_spi_sck_altcfg.afname = hal_spi_miso_altcfg.afname = hal_spi_mosi_altcfg.afname = afname;
hal_spi_sck_altcfg.afname = hal_spi_miso_altcfg.afmode = hal_spi_mosi_altcfg.afmode = afmode;
// configure miso, mosi, sck pins
memcpy(&config, &hal_brdcfg_spi__theconfig.gpio_sck[HAL_spi_id2index(id)].config, sizeof(hal_gpio_cfg_t));
config.altcfg = &hal_spi_sck_altcfg;
hal_gpio_init(hal_brdcfg_spi__theconfig.gpio_sck[HAL_spi_id2index(id)].gpio, &config);
memcpy(&config, &hal_brdcfg_spi__theconfig.gpio_miso[HAL_spi_id2index(id)].config, sizeof(hal_gpio_cfg_t));
config.altcfg = &hal_spi_miso_altcfg;
hal_gpio_init(hal_brdcfg_spi__theconfig.gpio_miso[HAL_spi_id2index(id)].gpio, &config);
memcpy(&config, &hal_brdcfg_spi__theconfig.gpio_mosi[HAL_spi_id2index(id)].config, sizeof(hal_gpio_cfg_t));
config.altcfg = &hal_spi_mosi_altcfg;
hal_gpio_init(hal_brdcfg_spi__theconfig.gpio_mosi[HAL_spi_id2index(id)].gpio, &config);
// hal_gpio_configure(hal_brdcfg_spi__theconfig.gpio_sck[HAL_spi_id2index(id)], &hal_spi_sck_altcfg);
// hal_gpio_configure(hal_brdcfg_spi__theconfig.gpio_miso[HAL_spi_id2index(id)], &hal_spi_miso_altcfg);
// hal_gpio_configure(hal_brdcfg_spi__theconfig.gpio_mosi[HAL_spi_id2index(id)], &hal_spi_mosi_altcfg);
#elif defined(HAL_USE_CPU_FAM_STM32F4)
static const GPIO_InitTypeDef s_hal_spi_misomosisck_altcfg =
{
.GPIO_Pin = 0,
.GPIO_Mode = GPIO_Mode_AF,
.GPIO_Speed = GPIO_Speed_50MHz,
.GPIO_OType = GPIO_OType_PP,
.GPIO_PuPd = GPIO_PuPd_DOWN
};
// 1. prepare af.
// for spi1 (sck, miso, mosi): sck -> PA5, PB3. miso -> PA6, PB4. mosi -> PA7, PB5.
// for spi2 (sck, miso, mosi): sck -> PB10, PB13, PI1. miso -> PAB14, PC2, PI2. mosi -> PB15, PC3, PI3.
// for spi3 (sck, miso, mosi): sck -> PB3, PC10. miso -> PB4, PC11. mosi -> PB5, PC12.
uint32_t afname = HAL_GPIO_AFNAME_NONE;
uint32_t afmode = HAL_GPIO_AFMODE_NONE;
hal_bool_t foundsck = hal_false;
hal_bool_t foundmiso = hal_false;
hal_bool_t foundmosi = hal_false;
hal_gpio_port_t portsck = hal_brdcfg_spi__theconfig.gpiomap[HAL_spi_id2index(id)].sck.gpio.port;
hal_gpio_pin_t pinsck = hal_brdcfg_spi__theconfig.gpiomap[HAL_spi_id2index(id)].sck.gpio.pin;
hal_gpio_port_t portmiso = hal_brdcfg_spi__theconfig.gpiomap[HAL_spi_id2index(id)].miso.gpio.port;
hal_gpio_pin_t pinmiso = hal_brdcfg_spi__theconfig.gpiomap[HAL_spi_id2index(id)].miso.gpio.pin;
hal_gpio_port_t portmosi = hal_brdcfg_spi__theconfig.gpiomap[HAL_spi_id2index(id)].mosi.gpio.port;
hal_gpio_pin_t pinmosi = hal_brdcfg_spi__theconfig.gpiomap[HAL_spi_id2index(id)].mosi.gpio.pin;
if(hal_spi1 == id)
{
afname = GPIO_AF_SPI1;
afmode = ENABLE;
if( ((hal_gpio_portA == portsck) && (hal_gpio_pin5 == pinsck)) ||
((hal_gpio_portB == portsck) && (hal_gpio_pin3 == pinsck)) )
{ // PA5, PB3
foundsck = hal_true;
}
if( ((hal_gpio_portA == portmiso) && (hal_gpio_pin6 == pinmiso)) ||
((hal_gpio_portB == portmiso) && (hal_gpio_pin4 == pinmiso)) )
{ // PA6, PB4
foundmiso = hal_true;
}
if( ((hal_gpio_portA == portmosi) && (hal_gpio_pin7 == pinmosi)) ||
((hal_gpio_portB == portmosi) && (hal_gpio_pin5 == pinmosi)) )
{ // PA7, PB5
foundmosi = hal_true;
}
}
else if(hal_spi2 == id)
{
afname = GPIO_AF_SPI2;
afmode = ENABLE;
if( ((hal_gpio_portB == portsck) && (hal_gpio_pin10 == pinsck)) ||
((hal_gpio_portB == portsck) && (hal_gpio_pin13 == pinsck)) ||
((hal_gpio_portI == portsck) && (hal_gpio_pin1 == pinsck)) )
{ // PB10, PB13, PI1
foundsck = hal_true;
}
if( ((hal_gpio_portB == portmiso) && (hal_gpio_pin14 == pinmiso)) ||
((hal_gpio_portC == portmiso) && (hal_gpio_pin2 == pinmiso)) ||
((hal_gpio_portI == portmiso) && (hal_gpio_pin2 == pinmiso)) )
{ // PAB14, PC2, PI2
foundmiso = hal_true;
}
if( ((hal_gpio_portB == portmosi) && (hal_gpio_pin15 == pinmosi)) ||
((hal_gpio_portC == portmosi) && (hal_gpio_pin3 == pinmosi)) ||
((hal_gpio_portI == portmosi) && (hal_gpio_pin3 == pinmosi)) )
{ // PB15, PC3, PI3
foundmosi = hal_true;
}
}
else if(hal_spi3 == id)
{
afname = GPIO_AF_SPI3;
afmode = ENABLE;
if( ((hal_gpio_portB == portsck) && (hal_gpio_pin3 == pinsck)) ||
((hal_gpio_portC == portsck) && (hal_gpio_pin10 == pinsck)) )
{ // PB3, PC10
foundsck = hal_true;
}
if( ((hal_gpio_portB == portmiso) && (hal_gpio_pin4 == pinmiso)) ||
((hal_gpio_portC == portmiso) && (hal_gpio_pin11 == pinmiso)) )
{ // PB4, PC11
foundmiso = hal_true;
}
if( ((hal_gpio_portB == portmosi) && (hal_gpio_pin5 == pinmosi)) ||
((hal_gpio_portC == portmosi) && (hal_gpio_pin12 == pinmosi)) )
{ // PB5, PC12
foundmosi = hal_true;
}
}
if((hal_false == foundsck) || (hal_false == foundmiso) || (hal_false == foundmosi))
{
hal_base_on_fatalerror(hal_fatalerror_incorrectparameter, "hal_spi_init(): incorrect pin mapping");
}
hal_gpio_cfg_t hal_spi_sck_cfg;
hal_gpio_cfg_t hal_spi_miso_cfg;
hal_gpio_cfg_t hal_spi_mosi_cfg;
hal_gpio_altcfg_t hal_spi_sck_altcfg;
hal_gpio_altcfg_t hal_spi_miso_altcfg;
hal_gpio_altcfg_t hal_spi_mosi_altcfg;
// prepare the altcfg for sck miso mosi pins
memcpy(&hal_spi_sck_altcfg.gpioext, &s_hal_spi_misomosisck_altcfg, sizeof(GPIO_InitTypeDef));
memcpy(&hal_spi_miso_altcfg.gpioext, &s_hal_spi_misomosisck_altcfg, sizeof(GPIO_InitTypeDef));
memcpy(&hal_spi_mosi_altcfg.gpioext, &s_hal_spi_misomosisck_altcfg, sizeof(GPIO_InitTypeDef));
hal_spi_sck_altcfg.afname = hal_spi_miso_altcfg.afname = hal_spi_mosi_altcfg.afname = afname;
hal_spi_sck_altcfg.afmode = hal_spi_miso_altcfg.afmode = hal_spi_mosi_altcfg.afmode = afmode;
// the gpiocfgs.
hal_spi_sck_cfg.dir = hal_gpio_dirALT;
hal_spi_sck_cfg.speed = hal_gpio_speed_default;
hal_spi_sck_cfg.altcfg = &hal_spi_sck_altcfg;
hal_spi_miso_cfg.dir = hal_gpio_dirALT;
hal_spi_miso_cfg.speed = hal_gpio_speed_default;
hal_spi_miso_cfg.altcfg = &hal_spi_miso_altcfg;
hal_spi_mosi_cfg.dir = hal_gpio_dirALT;
hal_spi_mosi_cfg.speed = hal_gpio_speed_default;
hal_spi_mosi_cfg.altcfg = &hal_spi_mosi_altcfg;
// configure sck miso mosi pins
hal_gpio_init(hal_brdcfg_spi__theconfig.gpiomap[HAL_spi_id2index(id)].sck.gpio, &hal_spi_sck_cfg);
hal_gpio_init(hal_brdcfg_spi__theconfig.gpiomap[HAL_spi_id2index(id)].miso.gpio, &hal_spi_miso_cfg);
hal_gpio_init(hal_brdcfg_spi__theconfig.gpiomap[HAL_spi_id2index(id)].mosi.gpio, &hal_spi_mosi_cfg);
#else //defined(HAL_USE_CPU_FAM_*)
#error ERR --> choose a HAL_USE_CPU_FAM_*
#endif
}
static void s_hal_spi_hw_enable(hal_spi_t id, const hal_spi_cfg_t* cfg)
{
#if defined(HAL_USE_CPU_FAM_STM32F1) || defined(HAL_USE_CPU_FAM_STM32F4)
SPI_TypeDef* SPIx = HAL_spi_id2stmSPI(id);
uint16_t prescaler_stm32fx = 0;
SPI_InitTypeDef spi_cfg;
SPI_I2S_DeInit(SPIx);
memcpy(&spi_cfg, &s_hal_spi_stm32_cfg, sizeof(SPI_InitTypeDef));
// apply the mode
spi_cfg.SPI_Mode = (hal_spi_ownership_master == cfg->ownership) ? (SPI_Mode_Master) : (SPI_Mode_Slave);
// configure speed of spi ...
if((hal_spi_speed_dontuse == cfg->speed) && (hal_spi_prescaler_dontuse == cfg->prescaler))
{
hal_base_on_fatalerror(hal_fatalerror_incorrectparameter, "hal_spi_init(): use one of speed or prescaler");
}
if((hal_spi_speed_dontuse != cfg->speed) && (hal_spi_prescaler_dontuse != cfg->prescaler))
{
hal_base_on_fatalerror(hal_fatalerror_incorrectparameter, "hal_spi_init(): use either speed or prescaler, not both");
}
if(hal_spi_prescaler_dontuse != cfg->prescaler)
{ // ok, we have the prescaler. need only to convert it in stm32fx format
switch(cfg->prescaler)
{ // remember that hal_spi_prescaler_xxx is referred to high speed bus,
// and prescaler_stm32fx to high speed bus for spi1 but to low speed for spi2 and spi3
case hal_spi_prescaler_004:
{
prescaler_stm32fx = (hal_spi1 == id) ? SPI_BaudRatePrescaler_4 : SPI_BaudRatePrescaler_2;
}
break;
case hal_spi_prescaler_008:
{
prescaler_stm32fx = (hal_spi1 == id) ? SPI_BaudRatePrescaler_8 : SPI_BaudRatePrescaler_4;
}
break;
case hal_spi_prescaler_016:
{
prescaler_stm32fx = (hal_spi1 == id) ? SPI_BaudRatePrescaler_16 : SPI_BaudRatePrescaler_8;
}
break;
case hal_spi_prescaler_032:
{
prescaler_stm32fx = (hal_spi1 == id) ? SPI_BaudRatePrescaler_32 : SPI_BaudRatePrescaler_16;
}
break;
case hal_spi_prescaler_064:
{
prescaler_stm32fx = (hal_spi1 == id) ? SPI_BaudRatePrescaler_64 : SPI_BaudRatePrescaler_32;
}
break;
case hal_spi_prescaler_128:
{
prescaler_stm32fx = (hal_spi1 == id) ? SPI_BaudRatePrescaler_128 : SPI_BaudRatePrescaler_64;
}
break;
case hal_spi_prescaler_256:
{
prescaler_stm32fx = (hal_spi1 == id) ? SPI_BaudRatePrescaler_256 : SPI_BaudRatePrescaler_128;
}
break;
default:
{
prescaler_stm32fx = SPI_BaudRatePrescaler_256;
}
break;
}
}
else if(hal_spi_speed_dontuse != cfg->speed)
{ // ok, use the speed to compute the prescaler in stm32fx format
// remember that hal_spi_prescaler_xxx is referred to high speed bus,
// and prescaler_stm32fx to high speed bus for spi1 but to low speed for spi2 and spi3
uint16_t factor = (hal_spi1 == id) ? (hal_brdcfg_cpu__theconfig.speeds.fastbus / cfg->speed) : (hal_brdcfg_cpu__theconfig.speeds.slowbus / cfg->speed);
switch(factor)
{
case 2:
prescaler_stm32fx = SPI_BaudRatePrescaler_2;
break;
case 4:
prescaler_stm32fx = SPI_BaudRatePrescaler_4;
break;
case 8:
prescaler_stm32fx = SPI_BaudRatePrescaler_8;
break;
case 16:
prescaler_stm32fx = SPI_BaudRatePrescaler_16;
break;
case 32:
prescaler_stm32fx = SPI_BaudRatePrescaler_32;
break;
case 64:
prescaler_stm32fx = SPI_BaudRatePrescaler_64;
break;
case 128:
prescaler_stm32fx = SPI_BaudRatePrescaler_128;
break;
case 256:
prescaler_stm32fx = SPI_BaudRatePrescaler_256;
break;
default:
prescaler_stm32fx = SPI_BaudRatePrescaler_256;
break;
}
}
// ok ... we have prescaler_stm32fx at last.
spi_cfg.SPI_BaudRatePrescaler = prescaler_stm32fx;
// can init spi
SPI_Init(SPIx, &spi_cfg);
if(hal_spi_act_framebased == cfg->activity)
{
// enable dma rx request
SPI_I2S_DMACmd(SPIx, SPI_I2S_DMAReq_Rx, ENABLE);
// enable dma tx request
SPI_I2S_DMACmd(SPIx, SPI_I2S_DMAReq_Tx, ENABLE);
}
#else //defined(HAL_USE_CPU_FAM_*)
#error ERR --> choose a HAL_USE_CPU_FAM_*
#endif
}
static hal_result_t s_hal_spi_timeoutexpired(void)
{
hal_base_on_fatalerror(hal_fatalerror_incorrectparameter, "timeout error in spi raw operations");
return(hal_res_NOK_generic);
}
#if 0
static void s_hal_spi_scheduling_suspend(void)
{
hal_base_osal_scheduling_suspend();
}
static void s_hal_spi_scheduling_restart(void)
{
hal_base_osal_scheduling_restart();
}
#endif
static hal_result_t s_hal_spi_put(hal_spi_t id, uint8_t* txframe)
{
hal_result_t res = hal_res_NOK_generic;
hal_spi_internal_item_t* intitem = s_hal_spi_theinternals.items[HAL_spi_id2index(id)];
hal_spi_cfg_t* cfg = &intitem->config;
if(hal_spi_act_framebased != cfg->activity)
{
return(hal_res_NOK_generic);
}
if(hal_spi_dir_rxonly != cfg->direction)
{
// disable so that we can change a data structure which is used by the isr
hal_bool_t dmaisenabled = s_hal_spi_is_dma_enabled(id);
if(hal_true == dmaisenabled)
{
s_hal_spi_periph_dma_isr_disable(id);
}
res = hal_utility_fifo_put(&intitem->fifotx, txframe);
if(hal_true == dmaisenabled)
{
s_hal_spi_periph_dma_isr_enable(id);
}
}
// if(hal_true == sendnow)
// {
// // enable again
// s_hal_spi_periph_dma_enable(id);
// }
return(res);
}
static hal_result_t s_hal_spi_get(hal_spi_t id, uint8_t* rxframe, uint8_t* remainingrxframes)
{
hal_result_t res = hal_res_NOK_generic;
hal_spi_internal_item_t* intitem = s_hal_spi_theinternals.items[HAL_spi_id2index(id)];
hal_spi_cfg_t* cfg = &intitem->config;
if(hal_spi_act_framebased != cfg->activity)
{
return(hal_res_NOK_generic);
}
if(hal_spi_dir_txonly != intitem->config.direction)
{
hal_bool_t dmaisenabled = s_hal_spi_is_dma_enabled(id);
if(hal_true == dmaisenabled)
{
s_hal_spi_periph_dma_isr_disable(id);
}
res = hal_utility_fifo_get(&intitem->fiforx, rxframe, remainingrxframes);
if(hal_true == dmaisenabled)
{
s_hal_spi_periph_dma_isr_enable(id);
}
}
// if(NULL != size)
// {
// *size = (hal_res_OK == res) ? (s_hal_spi_internals[HAL_spi_id2index(id)].config.sizeofframe) : (0);
// }
// enable again
// s_hal_spi_isr_enable(id);
return(res);
}
static void s_hal_spi_periph_dma_isr_enable(hal_spi_t id)
{
hal_dma_isr_enable(s_hal_spi_dma_port2use_rx[HAL_spi_id2index(id)]);
hal_dma_isr_enable(s_hal_spi_dma_port2use_tx[HAL_spi_id2index(id)]);
}
/**
* gpio irq init
*
* Initialize an external interrupt on a gpio pin
*
* @param pin Pin number to enable gpio.
* @param handler Interrupt handler
* @param arg Argument to pass to interrupt handler
* @param trig Trigger mode of interrupt
* @param pull Push/pull mode of input.
*
* @return int
*/
int
gpio_irq_init(int pin, gpio_irq_handler_t handler, void *arg,
gpio_irq_trig_t trig, gpio_pull_t pull)
{
int rc;
int irqn;
int index;
uint32_t pin_mask;
uint32_t mode;
GPIO_InitTypeDef init_cfg;
/* Configure the gpio for an external interrupt */
rc = 0;
switch (trig) {
case GPIO_TRIG_NONE:
rc = -1;
break;
case GPIO_TRIG_RISING:
mode = GPIO_MODE_IT_RISING;
break;
case GPIO_TRIG_FALLING:
mode = GPIO_MODE_IT_FALLING;
break;
case GPIO_TRIG_BOTH:
mode = GPIO_MODE_IT_RISING_FALLING;
break;
case GPIO_TRIG_LOW:
rc = -1;
break;
case GPIO_TRIG_HIGH:
rc = -1;
break;
default:
rc = -1;
break;
}
/* Check to make sure no error has occurred */
if (!rc) {
/* Disable interrupt and clear any pending */
gpio_irq_disable(pin);
pin_mask = GPIO_MASK(pin);
__HAL_GPIO_EXTI_CLEAR_FLAG(pin_mask);
/* Set the gpio irq handler */
index = GPIO_INDEX(pin);
gpio_irq_handlers[index].isr = handler;
gpio_irq_handlers[index].arg = arg;
/* Configure the GPIO */
init_cfg.Mode = mode;
init_cfg.Pull = pull;
rc = hal_gpio_init(pin, &init_cfg);
if (!rc) {
/* Enable interrupt vector in NVIC */
irqn = hal_gpio_pin_to_irq(pin);
hal_gpio_set_nvic(irqn);
}
}
return rc;
}
static hal_result_t s_hal_brdcfg_device_eeprom__wp_init(void)
{
const hal_gpio_map_t* map = &hal_brdcfg_device_eeprom__gpiomapof_wp;
return(hal_gpio_init(map->gpio, &map->config));
}
