int test_timer_slice(void)
{
u32 low=0,high=0;
if(mdrv_timer_get_accuracy_timestamp(&high,&low))
return -1;
else{
hardtimer_print_error("low =0x%x\n",low);
hardtimer_print_error("high =0x%x\n",high);
}
return 0;
}
int slice_init(void){
struct device_node *node = NULL;
void *iomap_node = NULL;
u32 remap_flag=0;
s32 ret = 0;
/*p532 fpga 与p532 asic读取同一套dts，所以通过版本号区分slice来源;
* porting timer slice also source timer*/
if(BSP_BOARD_TYPE_SOC == bsp_get_version_info()->board_type|| \
BSP_BOARD_TYPE_SFT == bsp_get_version_info()->board_type)
{
node = of_find_compatible_node(NULL, NULL, "hisilicon,timer_stamp_mdm");
}
else
{
node = of_find_compatible_node(NULL, NULL, "hisilicon,timer_slice_mdm");
}
if(!node)
{
hardtimer_print_error("timer slice/stamp of_find_compatible_node failed.\r\n");
return BSP_ERROR;
}
if(!of_device_is_available(node)){
hardtimer_print_error("timer slice dts status is not ok.\n");
return BSP_ERROR;
}
ret = of_property_read_u32(node, "increase_count_flag", ×lice_ctrl.slice_is_increase);
ret |= of_property_read_u32_array(node, "offset", timeslice_ctrl.slice_offset, 2);
ret |= of_property_read_u32(node, "clock-frequency", ×lice_ctrl.slice_clock_freq);
ret |= of_property_read_u32(node, "reg", (u32*)×lice_ctrl.timerslice_base_addr_phy);
if(ret)
{
hardtimer_print_error("timer slice property get failed.\r\n");
return BSP_ERROR;
}
if(of_property_read_u32(node, "need_map", &remap_flag))
{
hardtimer_print_error("timer slice need_map get failed.\n");
return BSP_ERROR;
}
if(remap_flag){
iomap_node = of_iomap(node, 0);
if (NULL == iomap_node)
{
hardtimer_print_error("timer slice of_iomap failed.\n");
return BSP_ERROR;
}
timeslice_ctrl.timerslice_base_addr=(u32)iomap_node;
}
else
timeslice_ctrl.timerslice_base_addr=timeslice_ctrl.timerslice_base_addr_phy;
return BSP_OK;
}
int bsp_slice_init(void)
{
int ret = 0;
ret=slice_init();
ret|=hrt_slice_init();
if(ret){
hardtimer_print_error("failed.\n");
return BSP_ERROR;
}
timeslice_ctrl.is_inited_flag = 1;
hardtimer_print_error("ok.\n");
return BSP_OK;
}
void adp_timer_init(void)
{
s32 ret = 0;
ret = request_irq(adp_timer_ctrl[TIMER_CCPU_DSP_DRX_PROT_ID].int_num, (irq_handler_t)adp_timer_handler,0,"ccpu osa ",(void*)TIMER_CCPU_DSP_DRX_PROT_ID);
if(ret)
{
hardtimer_print_error("TIMER_CCPU_DSP_DRX_PROT_ID request_irq failed\n");
return;
}
ret = request_irq(adp_timer_ctrl[TIMER_DSP_TIMER2_ID].int_num, (irq_handler_t)adp_timer_handler,0," ccpu dsp2",(void*)TIMER_DSP_TIMER2_ID);
if(ret)
{
hardtimer_print_error("TIMER_DSP_TIMER2_ID request_irq failed\n");
return;
}
ret = request_irq(adp_timer_ctrl[TIMER_DSP_TIMER1_ID].int_num, (irq_handler_t)adp_timer_handler,0," ccpu dsp1",(void*)TIMER_DSP_TIMER1_ID);
if(ret)
{
hardtimer_print_error("TIMER_DSP_TIMER1_ID request_irq failed\n");
return;
}
ret = request_irq(adp_timer_ctrl[TIMER_CCPU_OSA_ID].int_num, (irq_handler_t)adp_timer_handler,0," ccpu osa",(void*)TIMER_CCPU_OSA_ID);
if(ret)
{
hardtimer_print_error("TIMER_CCPU_OSA_ID request_irq failed\n");
return;
}
ret = request_irq(adp_timer_ctrl[TIMER_CCPU_DRX1_STABLE_ID].int_num, (irq_handler_t)adp_timer_handler,0," ccpu drx1",(void*)TIMER_CCPU_DRX1_STABLE_ID);
if(ret)
{
hardtimer_print_error("TIMER_CCPU_DRX1_STABLE_ID request_irq failed\n");
return;
}
ret = request_irq(adp_timer_ctrl[TIMER_CCPU_DRX_TIMER_ID].int_num, (irq_handler_t)adp_timer_handler,0," ccpu drx1",(void*)TIMER_CCPU_DRX_TIMER_ID);
if(ret)
{
hardtimer_print_error("TIMER_CCPU_DRX_TIMER_ID request_irq failed\n");
return;
}
ret = request_irq(adp_timer_ctrl[TIMER_DSP_SWITCH_DELAY_ID].int_num, (irq_handler_t)adp_timer_handler,0," ccpu dsp awitch",(void*)TIMER_DSP_SWITCH_DELAY_ID);
if(ret)
{
hardtimer_print_error("TIMER_DSP_SWITCH_DELAY_ID request_irq failed\n");
return;
}
#ifndef K3_TIMER_FEATURE
ret = request_irq(adp_timer_ctrl[TIMER_CCPU_DRX2_STABLE_ID].int_num, (irq_handler_t)adp_timer_handler,0," ccpu drx1",(void*)TIMER_CCPU_DRX2_STABLE_ID);
if(ret)
{
hardtimer_print_error("TIMER_CCPU_DRX2_STABLE_ID request_irq failed\n");
return;
}
#endif
hardtimer_print_error("adp_timer_init ok\n");
}
static int adp_timer_init(void)
{
int ret = 0;
ret = request_irq(adp_timer_ctrl[TIMER_ACPU_OSA_ID].int_num,adp_timer_handler,IRQF_NO_SUSPEND," acpu osa",(void*)TIMER_ACPU_OSA_ID);
if(ret)
{
hardtimer_print_error("TIMER_ACPU_OSA_ID request_irq failed\n");
return -1;
}
ret = request_irq(adp_timer_ctrl[TIMER_ACPU_OM_TCXO_ID].int_num,adp_timer_handler,0," acpu osa",(void*)TIMER_ACPU_OM_TCXO_ID);
if(ret)
{
hardtimer_print_error("TIMER_ACPU_OSA_ID request_irq failed\n");
return -1;
}
register_syscore_ops(&debug_timer_dpm_ops);
hardtimer_print_error("adp_timer_init ok\n");
return 0;
}
int hrt_slice_init(void){
struct device_node *node = NULL;
char* hrttimer_slice = "hisilicon,hrttimer_slice_mdm";
void *iomap_node = NULL;
u32 remap_flag=0;
s32 ret = 0;
node = of_find_compatible_node(NULL, NULL, hrttimer_slice);
if(!node)
{
hardtimer_print_error("timer_hrtslice of_find_compatible_node failed.\n");
return BSP_ERROR;
}
if(!of_device_is_available(node)){
hardtimer_print_error("timer hrtslice dts status is not ok.\n");
return BSP_ERROR;
}
ret = of_property_read_u32(node, "increase_count_flag", ×lice_ctrl.hrt_slice_is_increase);
ret |= of_property_read_u32(node, "clock-frequency", ×lice_ctrl.hrt_slice_clock_freq);
ret |= of_property_read_u32_array(node, "offset", timeslice_ctrl.hrt_slice_offset, 2);
if(ret)
{
hardtimer_print_error("timer_hrtslice get property failed.\n");
return BSP_ERROR;
}
if(of_property_read_u32(node, "need_map", &remap_flag))
{
hardtimer_print_error("need_map get failed in dts\n");
return BSP_ERROR;
}
if(remap_flag){
/* 内存映射，获得基址 */
iomap_node = of_iomap(node, 0);
if (NULL == iomap_node)
{
hardtimer_print_error("hrttimer_app of_iomap failed.\n");
return BSP_ERROR;
}
timeslice_ctrl.timerslice_hrt_base_addr = (u32)iomap_node;
}
else
{
if(of_property_read_u32(node, "reg", ×lice_ctrl.timerslice_hrt_base_addr))
{
hardtimer_print_error("timer hrtslice reg get failed.\r\n");
return BSP_ERROR;
}
}
return BSP_OK;
}
s32 bsp_hardtimer_alloc_k3(struct bsp_hardtimer_control *timer_ctrl)
{
u32 readValue = 0, intLev = 0, timerAddr = 0;
s32 ret = 0;
unsigned long flags = 0;
intLev = hard_timer_control[timer_ctrl->timerId].interrupt_num;
hard_timer_control[timer_ctrl->timerId].routine = timer_ctrl->func;
hard_timer_control[timer_ctrl->timerId].arg = timer_ctrl->para;
spin_lock_irqsave(&hard_timer_control[timer_ctrl->timerId].lock,flags);
(void)bsp_hardtimer_disable_k3_noirq(timer_ctrl->timerId);
timerAddr = hard_timer_control[timer_ctrl->timerId].ctrl_addr;
if (TIMER_ONCE_COUNT == timer_ctrl->mode)
{
readValue = readl(timerAddr);
writel(readValue|0x23,timerAddr);
}
else if(TIMER_FREERUN_COUNT == timer_ctrl->mode)
{
readValue = readl(timerAddr);
writel(readValue|0x22,timerAddr);
}
else if(TIMER_PERIOD_COUNT == timer_ctrl->mode)
{
readValue = readl(timerAddr);
writel(readValue|0x62,timerAddr);
}
bsp_hardtimer_load_value_k3(timer_ctrl->timerId,timer_ctrl->timeout);
spin_unlock_irqrestore(&hard_timer_control[timer_ctrl->timerId].lock,flags);
if(timer_ctrl->func)
{
ret = request_irq(intLev, (irq_handler_t)timer_ctrl->func, 0, "hard_timer_irq",(void *)(timer_ctrl->para));
if (ret)
{
hardtimer_print_error("request_irq error,ret = %d\n",ret);
return ERROR;
}
}
return OK;
}
