void kmain(multiboot_info_t* mbd, unsigned long magic)
{
if(magic != MULTIBOOT_BOOTLOADER_MAGIC) {
scrn_setmode(GREEN,BLACK);
scrn_print("Algo salio muy muy mal. No se que mas decirte.");
return;
}
scrn_cls();
scrn_setmode(GREEN,BLACK);
scrn_print("BIENVENIDO A juampiOS\n\t"
"Estamos trabajando para ofrecerle "
"el OS del futuro.\n");
scrn_print("INICIALIZANDO GDT...");
gdt_init();
gdt_flush();
scrn_print("OK\nINICIALIZANDO IDT PARA LAS EXCEPCIONES...");
initialize_exception_handlers();
idt_init_exceptions();
remap_pic();
scrn_print("OK\nINICIALIZANDO IDT PARA LAS INTERRUPCIONES Y SYSCALLS...");
irq_init_handlers();
syscalls_initialize();
idt_init_interrupts();
idt_init_syscalls();
idt_flush();
irq_sti_force();
scrn_printf("OK\nCHEQUEANDO ESTADO DE LOS MODULOS...");
scrn_printf("%u MODULOS CARGADOS\n",mbd->mods_count);
scrn_print("CHECKEANDO ESTADO DE LA MEMORIA\n");
// Chequeamos que la cantidad de memoria RAM presente.
if(mbd->flags & 1) {
scrn_printf("\tCantidad de RAM en el sistema:\n"
"\t\tLower: %u Kb, Upper: %u Kb\n",
mbd->mem_lower,mbd->mem_upper);
} else {
kernel_panic("Mapa de memoria de GRUB invalido");
}
scrn_print("INICIALIZANDO LAS ESTRUCTURAS DE MEMORIA DEL KERNEL...");
module_t* grub_modules = (module_t*) mbd->mods_addr;
uint kernel_end_addr = grub_modules[mbd->mods_count-1].mod_end;
// El mapa de memoria upper es a partir del primer megabyte ergo el primer
// lugar donde nos vamos de largo es 1024 kilobytes mas la memoria que dice GRUB
paging_init(kernel_end_addr, (1024+mbd->mem_upper)*1024);
scrn_printf("OK\n");
scrn_print("INICIALIZANDO DISCO ATA\n");
hdd_init();
scrn_printf("INICIALIZANDO FILESYSTEM MINIX\n");
init_disk_super_block();
keybuffer_init(1024);
scheduler_init();
void * buffer = (void *) grub_modules[0].mod_start;
jump_to_initial(buffer);
while(1) ;
}
inline void init_dev_modules() {
proc_init();
con_init("/disk/bin/screen_saver.pso");
serial_init();
hdd_init();
fs_init();
pipe_init();
}
int main(int argc, char **argv)
{
init_app(argc, argv, "osd");
event_init();
char *hdd_cfg = cfg_getstr("HDD_CONF_FILENAME", "etc/hdd.conf");
hdd_init(hdd_cfg);
char *self_host = cfg_getstr("OSD2CLIENT_LISTEN_HOST", "*");
int self_port = cfg_getint32("OSD2CLIENT_LISTEN_PORT", 9527);
rpc_client_setup(self_host, self_port, MACHINE_OSD);
struct evhttp *httpd;
char *listen_host = cfg_getstr("OSD2CLIENT_LISTEN_HOST", "*");
int port = cfg_getint32("OSD2CLIENT_LISTEN_PORT", 9527);
httpd = evhttp_start(listen_host, port);
if (httpd == NULL) {
logging(LOG_ERROR, "start server error %m");
exit(1);
} else {
printf("Start osd at %s:%d\n", listen_host, port);
}
evhttp_set_cb(httpd, "/shutdown", shutdown_handler, NULL);
evhttp_set_gencb(httpd, gen_handler, NULL);
struct timeval five_seconds = {2,0};
struct event *update_clustermap_event= event_new(NULL, -1, EV_PERSIST, update_clustermap_from_cmgr_on_timer_cb, NULL);
event_add(update_clustermap_event, &five_seconds);
event_dispatch();
evhttp_free(httpd);
return 0;
}
/**********************************************
kmain()
Punto de entrada de código C.
*************************************************/
kmain() {
int i, num;
// Paging.start(0x200000);
// init_malloc();
initialize_pics(0x20,0x70);
setup_IDT_entry(&idt[0x70], 0x08, (dword) & _rtc, ACS_INT, 0);
_cache_init();
hdd_init();
/* CARGA DE IDT CON LA RUTINA DE ATENCION DE IRQ0 */
setup_IDT_entry (&idt[0x00], 0x08, (dword)&_int_00_hand, ACS_INT, 0);
setup_IDT_entry (&idt[0x01], 0x08, (dword)&_int_01_hand, ACS_INT, 0);
setup_IDT_entry (&idt[0x02], 0x08, (dword)&_int_02_hand, ACS_INT, 0);
setup_IDT_entry (&idt[0x03], 0x08, (dword)&_int_03_hand, ACS_INT, 0);
setup_IDT_entry (&idt[0x04], 0x08, (dword)&_int_04_hand, ACS_INT, 0);
setup_IDT_entry (&idt[0x05], 0x08, (dword)&_int_05_hand, ACS_INT, 0);
setup_IDT_entry (&idt[0x06], 0x08, (dword)&_int_06_hand, ACS_INT, 0);
setup_IDT_entry (&idt[0x07], 0x08, (dword)&_int_07_hand, ACS_INT, 0);
setup_IDT_entry (&idt[0x08], 0x08, (dword)&_int_08_hand, ACS_INT, 0);
setup_IDT_entry (&idt[0x09], 0x08, (dword)&_int_09_hand, ACS_INT, 0);
setup_IDT_entry (&idt[0x0A], 0x08, (dword)&_int_0A_hand, ACS_INT, 0);
setup_IDT_entry (&idt[0x0B], 0x08, (dword)&_int_0B_hand, ACS_INT, 0);
setup_IDT_entry (&idt[0x0C], 0x08, (dword)&_int_0C_hand, ACS_INT, 0);
setup_IDT_entry (&idt[0x0D], 0x08, (dword)&_int_0D_hand, ACS_INT, 0);
setup_IDT_entry (&idt[0x0E], 0x08, (dword)&_int_0E_hand, ACS_INT, 0);
setup_IDT_entry (&idt[0x0F], 0x08, (dword)&_int_0F_hand, ACS_INT, 0);
setup_IDT_entry (&idt[0x10], 0x08, (dword)&_int_10_hand, ACS_INT, 0);
setup_IDT_entry (&idt[0x11], 0x08, (dword)&_int_11_hand, ACS_INT, 0);
setup_IDT_entry (&idt[0x12], 0x08, (dword)&_int_12_hand, ACS_INT, 0);
setup_IDT_entry (&idt[0x13], 0x08, (dword)&_int_13_hand, ACS_INT, 0);
setup_IDT_entry (&idt[0x14], 0x08, (dword)&_int_14_hand, ACS_INT, 0);
setup_IDT_entry (&idt[0x15], 0x08, (dword)&_int_15_hand, ACS_INT, 0);
setup_IDT_entry (&idt[0x16], 0x08, (dword)&_int_16_hand, ACS_INT, 0);
setup_IDT_entry (&idt[0x17], 0x08, (dword)&_int_17_hand, ACS_INT, 0);
setup_IDT_entry (&idt[0x18], 0x08, (dword)&_int_18_hand, ACS_INT, 0);
setup_IDT_entry (&idt[0x19], 0x08, (dword)&_int_19_hand, ACS_INT, 0);
setup_IDT_entry (&idt[0x1A], 0x08, (dword)&_int_1A_hand, ACS_INT, 0);
setup_IDT_entry (&idt[0x1B], 0x08, (dword)&_int_1B_hand, ACS_INT, 0);
setup_IDT_entry (&idt[0x1C], 0x08, (dword)&_int_1C_hand, ACS_INT, 0);
setup_IDT_entry (&idt[0x1D], 0x08, (dword)&_int_1D_hand, ACS_INT, 0);
setup_IDT_entry (&idt[0x1E], 0x08, (dword)&_int_1E_hand, ACS_INT, 0);
setup_IDT_entry (&idt[0x1F], 0x08, (dword)&_int_1F_hand, ACS_INT, 0);
// setup_IDT_entry (&idt[0x20], 0x08, (dword)&_int_20_hand, ACS_INT, 0);
// setup_IDT_entry (&idt[0x21], 0x08, (dword)&_int_21_hand, ACS_INT, 0);
setup_IDT_entry(&idt[0x20], 0x08, (dword) & _timer_tick_hand, ACS_INT, 0);
/* CARGA DE IDT CON LA RUTINA DE ATENCION DE IRQ1 */
setup_IDT_entry(&idt[0x21], 0x08, (dword) & _KB_hand, ACS_INT, 0);
/* CARGA DE IDT CON LA RUTINA DE ATENCION DE int80h */
setup_IDT_entry(&idt[0x80], 0x08, (dword) & _int_80_hand, ACS_INT, 0);
/* CARGA DE IDT CON LA RUTINA DE ATENCION DE int79h */
setup_IDT_entry(&idt[0x79], 0x08, (dword) & _int_79_hand, ACS_INT, 0);
/* Carga de IDTR */
idtr.base = 0;
idtr.base += (dword) & idt;
idtr.limit = sizeof(idt) - 1;
_lidt(&idtr);
Cli();
int rate = 0x06;
_outb(0x70, 0x0A); //set index to register A
char prev=_inb(0x71); //get initial value of register A
_outb(0x70, 0x0A); //reset index to A
_outb(0x71, (prev & 0xF0) | rate); //write only our rate to A. Note, rate is the bottom 4 bits.
init_paging();
scheduler_init();
/* Habilito interrupcion de timer tick*/
_mascaraPIC1(0xFC);
_mascaraPIC2(0xFE);
_outb(0x70, 0x0B); //set the index to register B
prev= _inb(0x71); //read the current value of register B
_outb(0x70, 0x0B); //set the index again(a read will reset the index to register D)
_outb(0x71, prev | 0x40); //write the previous value or'd with 0x40. This turns on bit 6 of register B
Sti();
idle = create_process("idle", idle_main, 0, 0, 0, 0, 0, 0, 0, NULL, 0);
// We soon exit out of here :)
while (1);
}
