static int hdmi_streamoff(struct hdmi_device *hdev)
{
struct device *dev = hdev->dev;
dev_dbg(dev, "%s\n", __func__);
if (hdev->hdcp_info.hdcp_enable && hdev->hdcp_info.hdcp_start)
hdcp_stop(hdev);
hdmi_audio_enable(hdev, 0);
hdmi_enable(hdev, 0);
hdmi_tg_enable(hdev, 0);
hdev->streaming = HDMI_STOP;
/* change the HPD interrupt: Internal -> External */
disable_irq(hdev->int_irq);
cancel_work_sync(&hdev->hpd_work);
hdmi_reg_set_ext_hpd(hdev);
enable_irq(hdev->ext_irq);
dev_info(hdev->dev, "HDMI interrupt changed to external\n");
hdmi_dumpregs(hdev, "streamoff");
return 0;
}
static int hdmi_streamoff(struct hdmi_device *hdev)
{
struct device *dev = hdev->dev;
struct hdmi_resources *res = &hdev->res;
dev_dbg(dev, "%s\n", __func__);
if (hdev->hdcp_info.hdcp_enable)
hdcp_stop(hdev);
hdmi_audio_enable(hdev, 0);
hdmi_enable(hdev, 0);
hdmi_tg_enable(hdev, 0);
/* pixel(vpll) clock is used for HDMI in config mode */
clk_disable(res->sclk_hdmi);
clk_set_parent(res->sclk_hdmi, res->sclk_pixel);
clk_enable(res->sclk_hdmi);
v4l2_subdev_call(hdev->phy_sd, video, s_stream, 0);
hdev->streaming = 0;
hdmi_dumpregs(hdev, "streamoff");
return 0;
}
static int hdmi_streamon(struct hdmi_device *hdev)
{
struct device *dev = hdev->dev;
int ret;
u32 val0, val1, val2;
dev_dbg(dev, "%s\n", __func__);
/* 3D test */
hdmi_set_infoframe(hdev);
/* set packets for audio */
hdmi_set_packets(hdev);
/* init audio */
#if defined(CONFIG_VIDEO_EXYNOS_HDMI_AUDIO_I2S)
hdmi_reg_i2s_audio_init(hdev);
#elif defined(CONFIG_VIDEO_EXYNOS_HDMI_AUDIO_SPDIF)
hdmi_reg_spdif_audio_init(hdev);
#endif
/* enbale HDMI audio */
if (hdev->audio_enable)
hdmi_audio_enable(hdev, 1);
hdmi_set_dvi_mode(hdev);
/* controls the pixel value limitation */
hdmi_reg_set_limits(hdev);
/* enable HDMI and timing generator */
hdmi_enable(hdev, 1);
hdmi_tg_enable(hdev, 1);
hdev->streaming = HDMI_STREAMING;
/* change the HPD interrupt: External -> Internal */
disable_irq(hdev->ext_irq);
cancel_delayed_work_sync(&hdev->hpd_work_ext);
hdmi_reg_set_int_hpd(hdev);
enable_irq(hdev->int_irq);
dev_info(hdev->dev, "HDMI interrupt changed to internal\n");
/* start HDCP if enabled */
if (hdev->hdcp_info.hdcp_enable) {
ret = hdcp_start(hdev);
if (ret)
return ret;
}
val0 = hdmi_read(hdev, HDMI_ACR_MCTS0);
val1 = hdmi_read(hdev, HDMI_ACR_MCTS1);
val2 = hdmi_read(hdev, HDMI_ACR_MCTS2);
dev_dbg(dev, "HDMI_ACR_MCTS0 : 0x%08x\n", val0);
dev_dbg(dev, "HDMI_ACR_MCTS1 : 0x%08x\n", val1);
dev_dbg(dev, "HDMI_ACR_MCTS2 : 0x%08x\n", val2);
hdmi_dumpregs(hdev, "streamon");
return 0;
}
static int hdmi_streamoff(struct hdmi_device *hdev)
{
struct device *dev = hdev->dev;
dev_dbg(dev, "%s\n", __func__);
hdmi_reg_set_ext_hpd(hdev);
// if (edid_supports_hdmi(hdev)) {
#if 1
if (hdev->hdcp_info.hdcp_enable && hdev->hdcp_info.hdcp_start)
hdcp_stop(hdev);
#endif
// }
hdmi_audio_enable(hdev, 0);
hdmi_enable(hdev, 0);
hdmi_tg_enable(hdev, 0);
hdev->streaming = HDMI_STOP;
hdmi_dumpregs(hdev, "streamoff");
return 0;
}
static int hdmi_streamon(struct hdmi_device *hdev)
{
struct device *dev = hdev->dev;
int ret;
u32 val0, val1, val2;
dev_dbg(dev, "%s\n", __func__);
/* 3D test */
hdmi_set_infoframe(hdev);
/* set packets for audio */
hdmi_set_packets(hdev);
/* init audio */
#if defined(CONFIG_VIDEO_EXYNOS_HDMI_AUDIO_I2S)
//printk("=============================> HDMI IIS\n");
hdmi_reg_i2s_audio_init(hdev);
#elif defined(CONFIG_VIDEO_EXYNOS_HDMI_AUDIO_SPDIF)
hdmi_reg_spdif_audio_init(hdev);
#endif
/* enbale HDMI audio */
if (hdev->audio_enable)
{
//printk("<+++++++++++++++++++++++++++++++++++++++++++ HDMI ENABLE\n");
hdmi_audio_enable(hdev, 1);
//printk("<+++++++++++++++++++++++++++++++++++++++++++ HDMI ENABLE\n");
}
hdmi_set_dvi_mode(hdev);
/* controls the pixel value limitation */
hdmi_reg_set_limits(hdev);
/* enable HDMI and timing generator */
hdmi_enable(hdev, 1);
hdmi_tg_enable(hdev, 1);
hdmi_reg_set_int_hpd(hdev);
hdev->streaming = HDMI_STREAMING;
// if (edid_supports_hdmi(hdev)) {
#if 1
/* start HDCP if enabled */
if (hdev->hdcp_info.hdcp_enable) {
ret = hdcp_start(hdev);
if (ret)
return ret;
}
#endif
// }
val0 = hdmi_read(hdev, HDMI_ACR_MCTS0);
val1 = hdmi_read(hdev, HDMI_ACR_MCTS1);
val2 = hdmi_read(hdev, HDMI_ACR_MCTS2);
dev_dbg(dev, "HDMI_ACR_MCTS0 : 0x%08x\n", val0);
dev_dbg(dev, "HDMI_ACR_MCTS1 : 0x%08x\n", val1);
dev_dbg(dev, "HDMI_ACR_MCTS2 : 0x%08x\n", val2);
hdmi_dumpregs(hdev, "streamon");
return 0;
}
static int hdmi_streamon(struct hdmi_device *hdev)
{
struct device *dev = hdev->dev;
struct hdmi_resources *res = &hdev->res;
int ret, tries;
u32 val0, val1, val2;
dev_dbg(dev, "%s\n", __func__);
hdev->streaming = 1;
ret = v4l2_subdev_call(hdev->phy_sd, video, s_stream, 1);
if (ret)
return ret;
/* waiting for HDMIPHY's PLL to get to steady state */
for (tries = 100; tries; --tries) {
if (is_hdmiphy_ready(hdev))
break;
mdelay(1);
}
/* steady state not achieved */
if (tries == 0) {
dev_err(dev, "hdmiphy's pll could not reach steady state.\n");
v4l2_subdev_call(hdev->phy_sd, video, s_stream, 0);
hdmi_dumpregs(hdev, "s_stream");
return -EIO;
}
/* hdmiphy clock is used for HDMI in streaming mode */
clk_disable(res->sclk_hdmi);
clk_set_parent(res->sclk_hdmi, res->sclk_hdmiphy);
clk_enable(res->sclk_hdmi);
/* 3D test */
hdmi_set_infoframe(hdev);
/* set packets for audio */
hdmi_set_packets(hdev);
/* init audio */
#if defined(CONFIG_VIDEO_EXYNOS_HDMI_AUDIO_I2S)
hdmi_reg_i2s_audio_init(hdev);
#elif defined(CONFIG_VIDEO_EXYNOS_HDMI_AUDIO_SPDIF)
hdmi_reg_spdif_audio_init(hdev);
#endif
/* enbale HDMI audio */
if (hdev->audio_enable)
hdmi_audio_enable(hdev, 1);
hdmi_set_dvi_mode(hdev);
/* enable HDMI and timing generator */
hdmi_enable(hdev, 1);
hdmi_tg_enable(hdev, 1);
mdelay(5);
val0 = hdmi_read(hdev, HDMI_ACR_MCTS0);
val1 = hdmi_read(hdev, HDMI_ACR_MCTS1);
val2 = hdmi_read(hdev, HDMI_ACR_MCTS2);
dev_dbg(dev, "HDMI_ACR_MCTS0 : 0x%08x\n", val0);
dev_dbg(dev, "HDMI_ACR_MCTS1 : 0x%08x\n", val1);
dev_dbg(dev, "HDMI_ACR_MCTS2 : 0x%08x\n", val2);
/* start HDCP if enabled */
if (hdev->hdcp_info.hdcp_enable) {
ret = hdcp_start(hdev);
if (ret)
return ret;
}
hdmi_dumpregs(hdev, "streamon");
return 0;
}