static void fb_set_mode(const struct video_timing *mode) { unsigned int clock_m, clock_d; fb_get_clock_md(mode->pixel_clock, &clock_m, &clock_d); hdmi_out0_fi_hres_write(mode->h_active); hdmi_out0_fi_hsync_start_write(mode->h_active + mode->h_sync_offset); hdmi_out0_fi_hsync_end_write(mode->h_active + mode->h_sync_offset + mode->h_sync_width); hdmi_out0_fi_hscan_write(mode->h_active + mode->h_blanking); hdmi_out0_fi_vres_write(mode->v_active); hdmi_out0_fi_vsync_start_write(mode->v_active + mode->v_sync_offset); hdmi_out0_fi_vsync_end_write(mode->v_active + mode->v_sync_offset + mode->v_sync_width); hdmi_out0_fi_vscan_write(mode->v_active + mode->v_blanking); hdmi_out0_fi_length_write(mode->h_active*mode->v_active*2); hdmi_out1_fi_hres_write(mode->h_active); hdmi_out1_fi_hsync_start_write(mode->h_active + mode->h_sync_offset); hdmi_out1_fi_hsync_end_write(mode->h_active + mode->h_sync_offset + mode->h_sync_width); hdmi_out1_fi_hscan_write(mode->h_active + mode->h_blanking); hdmi_out1_fi_vres_write(mode->v_active); hdmi_out1_fi_vsync_start_write(mode->v_active + mode->v_sync_offset); hdmi_out1_fi_vsync_end_write(mode->v_active + mode->v_sync_offset + mode->v_sync_width); hdmi_out1_fi_vscan_write(mode->v_active + mode->v_blanking); hdmi_out1_fi_length_write(mode->h_active*mode->v_active*2); fb_clkgen_write(0x1, clock_d-1); fb_clkgen_write(0x3, clock_m-1); hdmi_out0_driver_clocking_send_go_write(1); while(!(hdmi_out0_driver_clocking_status_read() & CLKGEN_STATUS_PROGDONE)); while(!(hdmi_out0_driver_clocking_status_read() & CLKGEN_STATUS_LOCKED)); }
static void fb_clkgen_write(int cmd, int data) { int word; word = (data << 2) | cmd; hdmi_out0_driver_clocking_cmd_data_write(word); hdmi_out0_driver_clocking_send_cmd_data_write(1); while(hdmi_out0_driver_clocking_status_read() & CLKGEN_STATUS_BUSY); }
void pll_dump(void) { int i; #ifdef CSR_HDMI_OUT0_BASE printf("framebuffer PLL:\n"); for(i=0; i<32; i++) { hdmi_out0_driver_clocking_pll_adr_write(i); hdmi_out0_driver_clocking_pll_read_write(1); while(!hdmi_out0_driver_clocking_pll_drdy_read()); printf("%04x ", hdmi_out0_driver_clocking_pll_dat_r_read()); } printf("\n"); #endif #ifdef CSR_HDMI_IN0_BASE printf("dvisampler0 PLL:\n"); for(i=0; i<32; i++) { hdmi_in0_clocking_pll_adr_write(i); hdmi_in0_clocking_pll_read_write(1); while(!hdmi_in0_clocking_pll_drdy_read()); printf("%04x ", hdmi_in0_clocking_pll_dat_r_read()); } printf("\n"); #endif #ifdef CSR_HDMI_IN1_BASE printf("dvisampler1 PLL:\n"); for(i=0; i<32; i++) { hdmi_in1_clocking_pll_adr_write(i); hdmi_in1_clocking_pll_read_write(1); while(!hdmi_in1_clocking_pll_drdy_read()); printf("%04x ", hdmi_in1_clocking_pll_dat_r_read()); } printf("\n"); #endif printf("PLL_ADV status: 0x%1X\n", hdmi_out0_driver_clocking_status_read()); }